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tomse 2023-12-21 19:49:13 +01:00
commit 90c1eb256e
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248
AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 18v8_18v8
#
DEF 18v8_18v8 U 0 40 Y Y 1 F N
F0 "U" -100 650 50 H V C CNN
F1 "18v8_18v8" 0 750 50 H V C CNN
F2 "" -50 -500 50 H I C CNN
F3 "" -50 -500 50 H I C CNN
DRAW
S -300 550 300 -550 0 1 0 N
X I/CLK 1 -400 450 100 R 50 50 1 1 I
X GND 10 0 -650 100 U 50 50 1 1 I
X I 11 -400 -450 100 R 50 50 1 1 I
X I/O 12 400 -350 100 L 50 50 1 1 B
X I/O 13 400 -250 100 L 50 50 1 1 B
X I/O 14 400 -150 100 L 50 50 1 1 B
X I/O 15 400 -50 100 L 50 50 1 1 B
X I/O 16 400 50 100 L 50 50 1 1 B
X I/O 17 400 150 100 L 50 50 1 1 B
X I/O 18 400 250 100 L 50 50 1 1 B
X I/O 19 400 350 100 L 50 50 1 1 B
X I 2 -400 350 100 R 50 50 1 1 I
X VCC 20 0 650 100 D 50 50 1 1 W
X I 3 -400 250 100 R 50 50 1 1 I
X I 4 -400 150 100 R 50 50 1 1 I
X I 5 -400 50 100 R 50 50 1 1 I
X I 6 -400 -50 100 R 50 50 1 1 I
X I 7 -400 -150 100 R 50 50 1 1 I
X I 8 -400 -250 100 R 50 50 1 1 I
X I 9 -400 -350 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x05
#
DEF Connector_Generic_Conn_01x05 J 0 40 Y N 1 F N
F0 "J" 0 300 50 H V C CNN
F1 "Connector_Generic_Conn_01x05" 0 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 50 -250 1 1 10 f
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x06
#
DEF Connector_Generic_Conn_01x06 J 0 40 Y N 1 F N
F0 "J" 0 300 50 H V C CNN
F1 "Connector_Generic_Conn_01x06" 0 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 50 -350 1 1 10 f
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
X Pin_6 6 -200 -300 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Network08
#
DEF Device_R_Network08 RN 0 0 Y N 1 F N
F0 "RN" -500 0 50 V V C CNN
F1 "Device_R_Network08" 400 0 50 V V C CNN
F2 "Resistor_THT:R_Array_SIP9" 475 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R?Array?SIP*
$ENDFPLIST
DRAW
C -400 90 10 0 1 0 F
C -300 90 10 0 1 0 F
C -200 90 10 0 1 0 F
C -100 90 10 0 1 0 F
C 0 90 10 0 1 0 F
C 100 90 10 0 1 0 F
C 200 90 10 0 1 0 F
S -450 -125 350 125 0 1 10 f
S -430 60 -370 -100 0 1 10 N
S -330 60 -270 -100 0 1 10 N
S -230 60 -170 -100 0 1 10 N
S -130 60 -70 -100 0 1 10 N
S -30 60 30 -100 0 1 10 N
S 70 60 130 -100 0 1 10 N
S 170 60 230 -100 0 1 10 N
S 270 60 330 -100 0 1 10 N
P 2 0 1 0 -400 -100 -400 -150 N
P 2 0 1 0 -300 -100 -300 -150 N
P 2 0 1 0 -200 -100 -200 -150 N
P 2 0 1 0 -100 -100 -100 -150 N
P 2 0 1 0 0 -100 0 -150 N
P 2 0 1 0 100 -100 100 -150 N
P 2 0 1 0 200 -100 200 -150 N
P 2 0 1 0 300 -100 300 -150 N
P 4 0 1 0 -400 60 -400 90 -300 90 -300 60 N
P 4 0 1 0 -300 60 -300 90 -200 90 -200 60 N
P 4 0 1 0 -200 60 -200 90 -100 90 -100 60 N
P 4 0 1 0 -100 60 -100 90 0 90 0 60 N
P 4 0 1 0 0 60 0 90 100 90 100 60 N
P 4 0 1 0 100 60 100 90 200 90 200 60 N
P 4 0 1 0 200 60 200 90 300 90 300 60 N
X common 1 -400 200 100 D 50 50 1 1 P
X R1 2 -400 -200 50 U 50 50 1 1 P
X R2 3 -300 -200 50 U 50 50 1 1 P
X R3 4 -200 -200 50 U 50 50 1 1 P
X R4 5 -100 -200 50 U 50 50 1 1 P
X R5 6 0 -200 50 U 50 50 1 1 P
X R6 7 100 -200 50 U 50 50 1 1 P
X R7 8 200 -200 50 U 50 50 1 1 P
X R8 9 300 -200 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# amiga-chips_GARY
#
DEF amiga-chips_GARY U 0 40 Y Y 1 F N
F0 "U" 0 -50 60 H V C CNN
F1 "amiga-chips_GARY" 0 50 60 H V C CNN
F2 "" 50 300 60 H I C CNN
F3 "" 50 300 60 H I C CNN
DRAW
S 500 1200 -500 -1200 0 1 0 N
X VSS 1 -700 1150 200 R 50 50 1 1 W
X _LDS 10 -700 250 200 R 50 50 1 1 I I
X _UDS 11 -700 150 200 R 50 50 1 1 I I
X R/W 12 -700 50 200 R 50 50 1 1 I
X _AS 13 -700 -50 200 R 50 50 1 1 I I
X _BGACK 14 -700 -150 200 R 50 50 1 1 I I
X _DBR 15 -700 -250 200 R 50 50 1 1 I I
X _SEL0 16 -700 -350 200 R 50 50 1 1 I I
X VDD 17 -700 -450 200 R 50 50 1 1 W
X _RGAE 18 -700 -550 200 R 50 50 1 1 O I
X _BLS 19 -700 -650 200 R 50 50 1 1 O I
X _VPA 2 -700 1050 200 R 50 50 1 1 O I
X _RAME 20 -700 -750 200 R 50 50 1 1 O I
X _ROME 21 -700 -850 200 R 50 50 1 1 O I
X _RTCR 22 -700 -950 200 R 50 50 1 1 O I
X _RTCW 23 -700 -1050 200 R 50 50 1 1 O I
X VSS 24 -700 -1150 200 R 50 50 1 1 W
X _LATCH 25 700 -1150 200 L 50 50 1 1 I I
X _CDAC 26 700 -1050 200 L 50 50 1 1 O I
X CCKQ 27 700 -950 200 L 50 50 1 1 I
X CCK 28 700 -850 200 L 50 50 1 1 I
X _NOVR 29 700 -750 200 L 50 50 1 1 I I
X _CDR 3 -700 950 200 R 50 50 1 1 O I
X OVL 30 700 -650 200 L 50 50 1 1 I
X XRDY 31 700 -550 200 L 50 50 1 1 I
X _NEXP 32 700 -450 200 L 50 50 1 1 I I
X A17 33 700 -350 200 L 50 50 1 1 I
X A18 34 700 -250 200 L 50 50 1 1 I
X A19 35 700 -150 200 L 50 50 1 1 I
X A20 36 700 -50 200 L 50 50 1 1 I
X A21 37 700 50 200 L 50 50 1 1 I
X A22 38 700 150 200 L 50 50 1 1 I
X A23 39 700 250 200 L 50 50 1 1 I
X _CDW 4 -700 850 200 R 50 50 1 1 O I
X N/C 40 700 350 200 L 50 50 1 1 N
X _RST 41 700 450 200 L 50 50 1 1 O I
X _HLT 42 700 550 200 L 50 50 1 1 O I
X _DTACK 43 700 650 200 L 50 50 1 1 O I
X DKWEB 44 700 750 200 L 50 50 1 1 O
X DKWDB 45 700 850 200 L 50 50 1 1 O
X MTR0D 46 700 950 200 L 50 50 1 1 O
X MTRXD 47 700 1050 200 L 50 50 1 1 O
X VDD 48 700 1150 200 L 50 50 1 1 W
X _KRES 5 -700 750 200 R 50 50 1 1 I I
X VDD 6 -700 650 200 R 50 50 1 1 W
X _MTR 7 -700 550 200 R 50 50 1 1 I I
X _DKWD 8 -700 450 200 R 50 50 1 1 I I
X _DKWE 9 -700 350 200 R 50 50 1 1 I I
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

988
AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter.kicad_pcb Normal file
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(kicad_pcb (version 20171130) (host pcbnew "(5.1.10)-1")
(general
(thickness 1.6)
(drawings 14)
(tracks 204)
(zones 0)
(modules 7)
(nets 61)
)
(page A4)
(title_block
(title "Gary Adapter for AmiTech MaxiMem")
(date 2021-06-13)
(rev 1.0)
(company https://retro-commodore.eu)
(comment 4 "reversed by Tomse 2021")
)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
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(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
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(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 GND)
(net 2 VDD)
(net 3 "Net-(J1-Pad6)")
(net 4 "Net-(J1-Pad5)")
(net 5 "Net-(J1-Pad3)")
(net 6 "Net-(J1-Pad2)")
(net 7 "Net-(J1-Pad1)")
(net 8 "Net-(J2-Pad5)")
(net 9 "Net-(J2-Pad4)")
(net 10 "Net-(J2-Pad3)")
(net 11 "Net-(J2-Pad2)")
(net 12 "Net-(J2-Pad1)")
(net 13 "Net-(RN1-Pad5)")
(net 14 "Net-(RN1-Pad4)")
(net 15 "Net-(RN1-Pad3)")
(net 16 MTRXD)
(net 17 MTROD)
(net 18 "Net-(U1-Pad22)")
(net 19 DKWDB)
(net 20 "Net-(U1-Pad21)")
(net 21 DKWEB)
(net 22 ~DTACK)
(net 23 "Net-(U1-Pad19)")
(net 24 ~HLT)
(net 25 "Net-(U1-Pad18)")
(net 26 ~RST)
(net 27 "Net-(U1-Pad17)")
(net 28 "Net-(U1-Pad40)")
(net 29 "Net-(U1-Pad16)")
(net 30 A23)
(net 31 A22)
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(net 33 A21)
(net 34 "Net-(U1-Pad13)")
(net 35 /A20)
(net 36 "Net-(U1-Pad12)")
(net 37 /A19)
(net 38 "Net-(U1-Pad11)")
(net 39 A18)
(net 40 "Net-(U1-Pad10)")
(net 41 A17)
(net 42 "Net-(U1-Pad9)")
(net 43 ~NEXP)
(net 44 "Net-(U1-Pad8)")
(net 45 XRDY)
(net 46 "Net-(U1-Pad7)")
(net 47 OVL)
(net 48 "Net-(U1-Pad6)")
(net 49 ~NOVR)
(net 50 "Net-(U1-Pad5)")
(net 51 CCK)
(net 52 "Net-(U1-Pad4)")
(net 53 CCKQ)
(net 54 "Net-(U1-Pad3)")
(net 55 ~CDAC)
(net 56 "Net-(U1-Pad2)")
(net 57 ~LATCH)
(net 58 "Net-(U1-Pad1)")
(net 59 "Net-(U2-Pad40)")
(net 60 "Net-(U1-Pad23)")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net /A19)
(add_net /A20)
(add_net A17)
(add_net A18)
(add_net A21)
(add_net A22)
(add_net A23)
(add_net CCK)
(add_net CCKQ)
(add_net DKWDB)
(add_net DKWEB)
(add_net MTROD)
(add_net MTRXD)
(add_net "Net-(J1-Pad1)")
(add_net "Net-(J1-Pad2)")
(add_net "Net-(J1-Pad3)")
(add_net "Net-(J1-Pad5)")
(add_net "Net-(J1-Pad6)")
(add_net "Net-(J2-Pad1)")
(add_net "Net-(J2-Pad2)")
(add_net "Net-(J2-Pad3)")
(add_net "Net-(J2-Pad4)")
(add_net "Net-(J2-Pad5)")
(add_net "Net-(RN1-Pad3)")
(add_net "Net-(RN1-Pad4)")
(add_net "Net-(RN1-Pad5)")
(add_net "Net-(U1-Pad1)")
(add_net "Net-(U1-Pad10)")
(add_net "Net-(U1-Pad11)")
(add_net "Net-(U1-Pad12)")
(add_net "Net-(U1-Pad13)")
(add_net "Net-(U1-Pad14)")
(add_net "Net-(U1-Pad16)")
(add_net "Net-(U1-Pad17)")
(add_net "Net-(U1-Pad18)")
(add_net "Net-(U1-Pad19)")
(add_net "Net-(U1-Pad2)")
(add_net "Net-(U1-Pad21)")
(add_net "Net-(U1-Pad22)")
(add_net "Net-(U1-Pad23)")
(add_net "Net-(U1-Pad3)")
(add_net "Net-(U1-Pad4)")
(add_net "Net-(U1-Pad40)")
(add_net "Net-(U1-Pad5)")
(add_net "Net-(U1-Pad6)")
(add_net "Net-(U1-Pad7)")
(add_net "Net-(U1-Pad8)")
(add_net "Net-(U1-Pad9)")
(add_net "Net-(U2-Pad40)")
(add_net OVL)
(add_net XRDY)
(add_net ~CDAC)
(add_net ~DTACK)
(add_net ~HLT)
(add_net ~LATCH)
(add_net ~NEXP)
(add_net ~NOVR)
(add_net ~RST)
)
(net_class PWR ""
(clearance 0.2)
(trace_width 1)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net GND)
(add_net VDD)
)
(module Package_DIP:DIP-48_W15.24mm_LongPads (layer F.Cu) (tedit 60C66807) (tstamp 60C6CC0B)
(at 128.27 69.85)
(descr "48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads")
(tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads")
(path /60C91C09)
(fp_text reference U1 (at 7.62 -2.33) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Socket (at 7.62 60.75) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 7.62 29.21) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 48 thru_hole oval (at 15.24 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(net 1 GND))
(pad 47 thru_hole oval (at 15.24 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 MTRXD))
(pad 23 thru_hole oval (at 0 55.88) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 60 "Net-(U1-Pad23)"))
(pad 46 thru_hole oval (at 15.24 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 MTROD))
(pad 22 thru_hole oval (at 0 53.34) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 "Net-(U1-Pad22)"))
(pad 45 thru_hole oval (at 15.24 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 DKWDB))
(pad 21 thru_hole oval (at 0 50.8) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(U1-Pad21)"))
(pad 44 thru_hole oval (at 15.24 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 DKWEB))
(pad 20 thru_hole oval (at 0 48.26) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(J1-Pad6)"))
(pad 43 thru_hole oval (at 15.24 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 ~DTACK))
(pad 19 thru_hole oval (at 0 45.72) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U1-Pad19)"))
(pad 42 thru_hole oval (at 15.24 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 ~HLT))
(pad 18 thru_hole oval (at 0 43.18) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(U1-Pad18)"))
(pad 41 thru_hole oval (at 15.24 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 ~RST))
(pad 17 thru_hole oval (at 0 40.64) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 "Net-(U1-Pad17)"))
(pad 40 thru_hole oval (at 15.24 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 28 "Net-(U1-Pad40)"))
(pad 16 thru_hole oval (at 0 38.1) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 "Net-(U1-Pad16)"))
(pad 39 thru_hole oval (at 15.24 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 A23))
(pad 15 thru_hole oval (at 0 35.56) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(J1-Pad5)"))
(pad 38 thru_hole oval (at 15.24 25.4) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 A22))
(pad 14 thru_hole oval (at 0 33.02) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 "Net-(U1-Pad14)"))
(pad 37 thru_hole oval (at 15.24 27.94) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 A21))
(pad 13 thru_hole oval (at 0 30.48) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 "Net-(U1-Pad13)"))
(pad 36 thru_hole oval (at 15.24 30.48) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 35 /A20))
(pad 12 thru_hole oval (at 0 27.94) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 36 "Net-(U1-Pad12)"))
(pad 35 thru_hole oval (at 15.24 33.02) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 37 /A19))
(pad 11 thru_hole oval (at 0 25.4) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 38 "Net-(U1-Pad11)"))
(pad 34 thru_hole oval (at 15.24 35.56) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 39 A18))
(pad 10 thru_hole oval (at 0 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 40 "Net-(U1-Pad10)"))
(pad 33 thru_hole oval (at 15.24 38.1) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 41 A17))
(pad 9 thru_hole oval (at 0 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 42 "Net-(U1-Pad9)"))
(pad 32 thru_hole oval (at 15.24 40.64) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 43 ~NEXP))
(pad 8 thru_hole oval (at 0 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 44 "Net-(U1-Pad8)"))
(pad 31 thru_hole oval (at 15.24 43.18) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 45 XRDY))
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 46 "Net-(U1-Pad7)"))
(pad 30 thru_hole oval (at 15.24 45.72) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 47 OVL))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 48 "Net-(U1-Pad6)"))
(pad 29 thru_hole oval (at 15.24 48.26) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 49 ~NOVR))
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 50 "Net-(U1-Pad5)"))
(pad 28 thru_hole oval (at 15.24 50.8) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 51 CCK))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 "Net-(U1-Pad4)"))
(pad 27 thru_hole oval (at 15.24 53.34) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 CCKQ))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(U1-Pad3)"))
(pad 26 thru_hole oval (at 15.24 55.88) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 55 ~CDAC))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 56 "Net-(U1-Pad2)"))
(pad 25 thru_hole oval (at 15.24 58.42) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 57 ~LATCH))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 58 "Net-(U1-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x24_P2.54mm_Vertical.step
(offset (xyz 15.25 0 -2))
(scale (xyz 1 1 1))
(rotate (xyz 0 180 0))
)
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x24_P2.54mm_Vertical.step
(offset (xyz 0 0 -2))
(scale (xyz 1 1 1))
(rotate (xyz 0 180 0))
)
)
(module Package_DIP:DIP-20_W7.62mm_LongPads (layer F.Cu) (tedit 5A02E8C5) (tstamp 60C6CC77)
(at 152.4 87.63)
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads")
(path /60C83DE9)
(fp_text reference U3 (at 3.81 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 18v8 (at 3.81 25.19) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 11.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 24.19) (end 6.06 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 24.19) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.45 -1.55) (end -1.45 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 24.4) (end 9.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.1 24.4) (end 9.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.1 -1.55) (end -1.45 -1.55) (layer F.CrtYd) (width 0.05))
(pad 20 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 VDD))
(pad 10 thru_hole oval (at 0 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 19 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(RN1-Pad3)"))
(pad 9 thru_hole oval (at 0 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(J1-Pad2)"))
(pad 18 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(RN1-Pad4)"))
(pad 8 thru_hole oval (at 0 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 39 A18))
(pad 17 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(RN1-Pad5)"))
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 37 /A19))
(pad 16 thru_hole oval (at 7.62 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(J2-Pad5)"))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 35 /A20))
(pad 15 thru_hole oval (at 7.62 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(J2-Pad4)"))
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 A21))
(pad 14 thru_hole oval (at 7.62 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(J2-Pad3)"))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 A22))
(pad 13 thru_hole oval (at 7.62 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(J2-Pad2)"))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 A23))
(pad 12 thru_hole oval (at 7.62 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 "Net-(J2-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(RN1-Pad3)"))
(pad 11 thru_hole oval (at 7.62 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(J1-Pad3)"))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(J1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-48_W15.24mm_LongPads (layer F.Cu) (tedit 5A02E8C5) (tstamp 60C6CC4F)
(at 124.46 69.85)
(descr "48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads")
(tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads")
(path /60C88597)
(fp_text reference U2 (at 7.62 -2.33) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value GARY (at 7.62 60.75) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 7.62 29.21) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 -1.27) (end 14.985 59.69) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 59.69) (end 0.255 59.69) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 59.69) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.62 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 59.75) (end 13.68 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start 13.68 59.75) (end 13.68 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 13.68 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.5 -1.55) (end -1.5 59.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.5 59.95) (end 16.7 59.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.7 59.95) (end 16.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.7 -1.55) (end -1.5 -1.55) (layer F.CrtYd) (width 0.05))
(pad 48 thru_hole oval (at 15.24 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 VDD))
(pad 24 thru_hole oval (at 0 58.42) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 47 thru_hole oval (at 15.24 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 MTRXD))
(pad 23 thru_hole oval (at 0 55.88) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 60 "Net-(U1-Pad23)"))
(pad 46 thru_hole oval (at 15.24 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 MTROD))
(pad 22 thru_hole oval (at 0 53.34) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 "Net-(U1-Pad22)"))
(pad 45 thru_hole oval (at 15.24 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 DKWDB))
(pad 21 thru_hole oval (at 0 50.8) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(U1-Pad21)"))
(pad 44 thru_hole oval (at 15.24 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 DKWEB))
(pad 20 thru_hole oval (at 0 48.26) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(J1-Pad6)"))
(pad 43 thru_hole oval (at 15.24 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 ~DTACK))
(pad 19 thru_hole oval (at 0 45.72) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U1-Pad19)"))
(pad 42 thru_hole oval (at 15.24 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 ~HLT))
(pad 18 thru_hole oval (at 0 43.18) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(U1-Pad18)"))
(pad 41 thru_hole oval (at 15.24 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 ~RST))
(pad 17 thru_hole oval (at 0 40.64) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 "Net-(U1-Pad17)"))
(pad 40 thru_hole oval (at 15.24 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 59 "Net-(U2-Pad40)"))
(pad 16 thru_hole oval (at 0 38.1) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 "Net-(U1-Pad16)"))
(pad 39 thru_hole oval (at 15.24 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 A23))
(pad 15 thru_hole oval (at 0 35.56) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(J1-Pad5)"))
(pad 38 thru_hole oval (at 15.24 25.4) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 A22))
(pad 14 thru_hole oval (at 0 33.02) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 "Net-(U1-Pad14)"))
(pad 37 thru_hole oval (at 15.24 27.94) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 A21))
(pad 13 thru_hole oval (at 0 30.48) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 "Net-(U1-Pad13)"))
(pad 36 thru_hole oval (at 15.24 30.48) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(RN1-Pad5)"))
(pad 12 thru_hole oval (at 0 27.94) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 36 "Net-(U1-Pad12)"))
(pad 35 thru_hole oval (at 15.24 33.02) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(RN1-Pad4)"))
(pad 11 thru_hole oval (at 0 25.4) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 38 "Net-(U1-Pad11)"))
(pad 34 thru_hole oval (at 15.24 35.56) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 39 A18))
(pad 10 thru_hole oval (at 0 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 40 "Net-(U1-Pad10)"))
(pad 33 thru_hole oval (at 15.24 38.1) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 41 A17))
(pad 9 thru_hole oval (at 0 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 42 "Net-(U1-Pad9)"))
(pad 32 thru_hole oval (at 15.24 40.64) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 43 ~NEXP))
(pad 8 thru_hole oval (at 0 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 44 "Net-(U1-Pad8)"))
(pad 31 thru_hole oval (at 15.24 43.18) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 45 XRDY))
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 46 "Net-(U1-Pad7)"))
(pad 30 thru_hole oval (at 15.24 45.72) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 47 OVL))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 48 "Net-(U1-Pad6)"))
(pad 29 thru_hole oval (at 15.24 48.26) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 49 ~NOVR))
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 50 "Net-(U1-Pad5)"))
(pad 28 thru_hole oval (at 15.24 50.8) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 51 CCK))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 "Net-(U1-Pad4)"))
(pad 27 thru_hole oval (at 15.24 53.34) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 CCKQ))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(U1-Pad3)"))
(pad 26 thru_hole oval (at 15.24 55.88) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 55 ~CDAC))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 56 "Net-(U1-Pad2)"))
(pad 25 thru_hole oval (at 15.24 58.42) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 57 ~LATCH))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 58 "Net-(U1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-48_W15.24mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Array_SIP9 (layer F.Cu) (tedit 5A14249F) (tstamp 60C6CEF5)
(at 147.955 87.63 270)
(descr "9-pin Resistor SIP pack")
(tags R)
(path /60C861BD)
(fp_text reference RN1 (at 11.43 -2.4 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 11.43 2.4 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 10.16 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.29 -1.25) (end -1.29 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 1.25) (end 21.61 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 21.61 1.25) (end 21.61 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 21.61 -1.25) (end -1.29 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.25) (end 1.27 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.44 -1.4) (end -1.44 1.4) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 1.4) (end 21.76 1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 21.76 1.4) (end 21.76 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 21.76 -1.4) (end -1.44 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.4) (end 1.27 1.4) (layer F.SilkS) (width 0.12))
(fp_line (start -1.7 -1.65) (end -1.7 1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1.65) (end 22.05 1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 22.05 1.65) (end 22.05 -1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 22.05 -1.65) (end -1.7 -1.65) (layer F.CrtYd) (width 0.05))
(pad 9 thru_hole oval (at 20.32 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(J1-Pad2)"))
(pad 8 thru_hole oval (at 17.78 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(J1-Pad3)"))
(pad 7 thru_hole oval (at 15.24 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 "Net-(J2-Pad1)"))
(pad 6 thru_hole oval (at 12.7 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(J2-Pad2)"))
(pad 5 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(RN1-Pad5)"))
(pad 4 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(RN1-Pad4)"))
(pad 3 thru_hole oval (at 5.08 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(RN1-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(J1-Pad1)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 VDD))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Array_SIP9.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 60C6CBAB)
(at 163.83 107.95 180)
(descr "Through hole straight pin header, 1x05, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x05 2.54mm single row")
(path /60C63EE3)
(fp_text reference J2 (at 0 -2.33) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x05 (at 0 12.49) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 5.08 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 11.43) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 11.43) (end -1.27 11.43) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 11.43) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 11.49) (end 1.33 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 11.95) (end 1.8 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 11.95) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(pad 5 thru_hole oval (at 0 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 8 "Net-(J2-Pad5)"))
(pad 4 thru_hole oval (at 0 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 "Net-(J2-Pad4)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 10 "Net-(J2-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 11 "Net-(J2-Pad2)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 12 "Net-(J2-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x05_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 60C6D5C8)
(at 149.86 118.11 90)
(descr "Through hole straight pin header, 1x06, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x06 2.54mm single row")
(path /60D73F25)
(fp_text reference J1 (at 0 -2.33 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x06 (at 0 15.03 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 6.35) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 13.97) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 13.97) (end -1.27 13.97) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 13.97) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 14.03) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 14.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 14.5) (end 1.8 14.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 14.5) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 3 "Net-(J1-Pad6)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 "Net-(J1-Pad5)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 55 ~CDAC))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 5 "Net-(J1-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 6 "Net-(J1-Pad2)"))
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 7 "Net-(J1-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x06_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 60C6DA60)
(at 154.94 81.28)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3*2mm^2, Capacitor")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3mm width 2mm Capacitor")
(path /60C64C51)
(fp_text reference C1 (at 1.25 -2.25) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 0.1uF (at 1.25 2.25) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0) (layer F.Fab)
(effects (font (size 0.6 0.6) (thickness 0.09)))
)
(fp_line (start -0.25 -1) (end -0.25 1) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 1) (end 2.75 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 1) (end 2.75 -1) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 -1) (end -0.25 -1) (layer F.Fab) (width 0.1))
(fp_line (start -0.37 -1.12) (end 2.87 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -0.37 1.12) (end 2.87 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -0.37 -1.12) (end -0.37 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.37 1.055) (end -0.37 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.87 -1.12) (end 2.87 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start 2.87 1.055) (end 2.87 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 3.55 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.25) (end 3.55 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(pad 2 thru_hole circle (at 2.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 VDD))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W2.0mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(gr_text GARY (at 133.985 90.805 90) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text "to MEM" (at 165.1 113.03 90) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text "to CPU" (at 153.035 121.285) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text "Reversed by tomse 2021\nhttps://retro-commodore.eu\n" (at 163.195 81.28 90) (layer F.Cu)
(effects (font (size 1.3 1.3) (thickness 0.15)))
)
(gr_text "AmiTech, DK\nMaxiMem\n" (at 135.255 80.01 90) (layer B.Cu)
(effects (font (size 1.5 1.5) (thickness 0.2)) (justify mirror))
)
(gr_text "GARY\nadapter" (at 134.62 118.745 90) (layer B.Cu)
(effects (font (size 1.5 1.5) (thickness 0.2)) (justify mirror))
)
(gr_arc (start 165.1 129.54) (end 165.1 130.81) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_arc (start 121.92 129.54) (end 120.65 129.54) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_arc (start 121.92 67.945) (end 121.92 66.675) (angle -90) (layer Edge.Cuts) (width 0.05))
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(gr_line (start 165.1 66.675) (end 121.92 66.675) (layer Edge.Cuts) (width 0.05) (tstamp 60C6EB00))
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(gr_line (start 120.65 67.945) (end 120.65 129.54) (layer Edge.Cuts) (width 0.05))
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979
AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter.kicad_pcb-bak Normal file
View File

@ -0,0 +1,979 @@
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(page A4)
(title_block
(title "Gary Adapter for AmiTech MaxiMem")
(date 2021-06-13)
(rev 1.0)
(company https://retro-commodore.eu)
(comment 4 "reversed by Tomse 2021")
)
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(pad 31 thru_hole oval (at 15.24 43.18) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 45 XRDY))
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 46 "Net-(U1-Pad7)"))
(pad 30 thru_hole oval (at 15.24 45.72) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 47 OVL))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 48 "Net-(U1-Pad6)"))
(pad 29 thru_hole oval (at 15.24 48.26) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 49 ~NOVR))
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 50 "Net-(U1-Pad5)"))
(pad 28 thru_hole oval (at 15.24 50.8) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 51 CCK))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 "Net-(U1-Pad4)"))
(pad 27 thru_hole oval (at 15.24 53.34) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 CCKQ))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(U1-Pad3)"))
(pad 26 thru_hole oval (at 15.24 55.88) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 55 ~CDAC))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 56 "Net-(U1-Pad2)"))
(pad 25 thru_hole oval (at 15.24 58.42) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 57 ~LATCH))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 58 "Net-(U1-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x24_P2.54mm_Vertical.step
(offset (xyz 15.25 0 -2))
(scale (xyz 1 1 1))
(rotate (xyz 0 180 0))
)
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x24_P2.54mm_Vertical.step
(offset (xyz 0 0 -2))
(scale (xyz 1 1 1))
(rotate (xyz 0 180 0))
)
)
(module Package_DIP:DIP-20_W7.62mm_LongPads (layer F.Cu) (tedit 5A02E8C5) (tstamp 60C6CC77)
(at 152.4 87.63)
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads")
(path /60C83DE9)
(fp_text reference U3 (at 3.81 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 18v8 (at 3.81 25.19) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 11.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 24.19) (end 6.06 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 24.19) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.45 -1.55) (end -1.45 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 24.4) (end 9.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.1 24.4) (end 9.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.1 -1.55) (end -1.45 -1.55) (layer F.CrtYd) (width 0.05))
(pad 20 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 VDD))
(pad 10 thru_hole oval (at 0 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 19 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(RN1-Pad3)"))
(pad 9 thru_hole oval (at 0 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(J1-Pad2)"))
(pad 18 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(RN1-Pad4)"))
(pad 8 thru_hole oval (at 0 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 39 A18))
(pad 17 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(RN1-Pad5)"))
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 37 /A19))
(pad 16 thru_hole oval (at 7.62 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(J2-Pad5)"))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 35 /A20))
(pad 15 thru_hole oval (at 7.62 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(J2-Pad4)"))
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 A21))
(pad 14 thru_hole oval (at 7.62 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(J2-Pad3)"))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 A22))
(pad 13 thru_hole oval (at 7.62 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(J2-Pad2)"))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 A23))
(pad 12 thru_hole oval (at 7.62 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 "Net-(J2-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(RN1-Pad3)"))
(pad 11 thru_hole oval (at 7.62 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(J1-Pad3)"))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(J1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-48_W15.24mm_LongPads (layer F.Cu) (tedit 5A02E8C5) (tstamp 60C6CC4F)
(at 124.46 69.85)
(descr "48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads")
(tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads")
(path /60C88597)
(fp_text reference U2 (at 7.62 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value GARY (at 7.62 60.75) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 7.62 29.21) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 -1.27) (end 14.985 59.69) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 59.69) (end 0.255 59.69) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 59.69) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.62 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 59.75) (end 13.68 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start 13.68 59.75) (end 13.68 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 13.68 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.5 -1.55) (end -1.5 59.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.5 59.95) (end 16.7 59.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.7 59.95) (end 16.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.7 -1.55) (end -1.5 -1.55) (layer F.CrtYd) (width 0.05))
(pad 48 thru_hole oval (at 15.24 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 VDD))
(pad 24 thru_hole oval (at 0 58.42) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 47 thru_hole oval (at 15.24 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 MTRXD))
(pad 23 thru_hole oval (at 0 55.88) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 60 "Net-(U1-Pad23)"))
(pad 46 thru_hole oval (at 15.24 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 MTROD))
(pad 22 thru_hole oval (at 0 53.34) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 "Net-(U1-Pad22)"))
(pad 45 thru_hole oval (at 15.24 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 DKWDB))
(pad 21 thru_hole oval (at 0 50.8) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(U1-Pad21)"))
(pad 44 thru_hole oval (at 15.24 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 DKWEB))
(pad 20 thru_hole oval (at 0 48.26) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(J1-Pad6)"))
(pad 43 thru_hole oval (at 15.24 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 ~DTACK))
(pad 19 thru_hole oval (at 0 45.72) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U1-Pad19)"))
(pad 42 thru_hole oval (at 15.24 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 ~HLT))
(pad 18 thru_hole oval (at 0 43.18) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(U1-Pad18)"))
(pad 41 thru_hole oval (at 15.24 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 ~RST))
(pad 17 thru_hole oval (at 0 40.64) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 "Net-(U1-Pad17)"))
(pad 40 thru_hole oval (at 15.24 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 59 "Net-(U2-Pad40)"))
(pad 16 thru_hole oval (at 0 38.1) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 "Net-(U1-Pad16)"))
(pad 39 thru_hole oval (at 15.24 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 A23))
(pad 15 thru_hole oval (at 0 35.56) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(J1-Pad5)"))
(pad 38 thru_hole oval (at 15.24 25.4) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 A22))
(pad 14 thru_hole oval (at 0 33.02) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 "Net-(U1-Pad14)"))
(pad 37 thru_hole oval (at 15.24 27.94) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 A21))
(pad 13 thru_hole oval (at 0 30.48) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 "Net-(U1-Pad13)"))
(pad 36 thru_hole oval (at 15.24 30.48) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(RN1-Pad5)"))
(pad 12 thru_hole oval (at 0 27.94) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 36 "Net-(U1-Pad12)"))
(pad 35 thru_hole oval (at 15.24 33.02) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(RN1-Pad4)"))
(pad 11 thru_hole oval (at 0 25.4) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 38 "Net-(U1-Pad11)"))
(pad 34 thru_hole oval (at 15.24 35.56) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 39 A18))
(pad 10 thru_hole oval (at 0 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 40 "Net-(U1-Pad10)"))
(pad 33 thru_hole oval (at 15.24 38.1) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 41 A17))
(pad 9 thru_hole oval (at 0 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 42 "Net-(U1-Pad9)"))
(pad 32 thru_hole oval (at 15.24 40.64) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 43 ~NEXP))
(pad 8 thru_hole oval (at 0 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 44 "Net-(U1-Pad8)"))
(pad 31 thru_hole oval (at 15.24 43.18) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 45 XRDY))
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 46 "Net-(U1-Pad7)"))
(pad 30 thru_hole oval (at 15.24 45.72) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 47 OVL))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 48 "Net-(U1-Pad6)"))
(pad 29 thru_hole oval (at 15.24 48.26) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 49 ~NOVR))
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 50 "Net-(U1-Pad5)"))
(pad 28 thru_hole oval (at 15.24 50.8) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 51 CCK))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 "Net-(U1-Pad4)"))
(pad 27 thru_hole oval (at 15.24 53.34) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 CCKQ))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(U1-Pad3)"))
(pad 26 thru_hole oval (at 15.24 55.88) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 55 ~CDAC))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 56 "Net-(U1-Pad2)"))
(pad 25 thru_hole oval (at 15.24 58.42) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 57 ~LATCH))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 58 "Net-(U1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-48_W15.24mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Array_SIP9 (layer F.Cu) (tedit 5A14249F) (tstamp 60C6CEF5)
(at 147.955 87.63 270)
(descr "9-pin Resistor SIP pack")
(tags R)
(path /60C861BD)
(fp_text reference RN1 (at 11.43 -2.4 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 11.43 2.4 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 10.16 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.29 -1.25) (end -1.29 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 1.25) (end 21.61 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 21.61 1.25) (end 21.61 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 21.61 -1.25) (end -1.29 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.25) (end 1.27 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.44 -1.4) (end -1.44 1.4) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 1.4) (end 21.76 1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 21.76 1.4) (end 21.76 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 21.76 -1.4) (end -1.44 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.4) (end 1.27 1.4) (layer F.SilkS) (width 0.12))
(fp_line (start -1.7 -1.65) (end -1.7 1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1.65) (end 22.05 1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 22.05 1.65) (end 22.05 -1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 22.05 -1.65) (end -1.7 -1.65) (layer F.CrtYd) (width 0.05))
(pad 9 thru_hole oval (at 20.32 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(J1-Pad2)"))
(pad 8 thru_hole oval (at 17.78 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(J1-Pad3)"))
(pad 7 thru_hole oval (at 15.24 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 "Net-(J2-Pad1)"))
(pad 6 thru_hole oval (at 12.7 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(J2-Pad2)"))
(pad 5 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(RN1-Pad5)"))
(pad 4 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(RN1-Pad4)"))
(pad 3 thru_hole oval (at 5.08 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(RN1-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(J1-Pad1)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 VDD))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Array_SIP9.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 60C6CBAB)
(at 163.83 107.95 180)
(descr "Through hole straight pin header, 1x05, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x05 2.54mm single row")
(path /60C63EE3)
(fp_text reference J2 (at 0 -2.33) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x05 (at 0 12.49) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 5.08 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 11.43) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 11.43) (end -1.27 11.43) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 11.43) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 11.49) (end 1.33 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 11.95) (end 1.8 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 11.95) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(pad 5 thru_hole oval (at 0 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 8 "Net-(J2-Pad5)"))
(pad 4 thru_hole oval (at 0 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 "Net-(J2-Pad4)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 10 "Net-(J2-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 11 "Net-(J2-Pad2)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 12 "Net-(J2-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x05_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 60C6D5C8)
(at 149.86 118.11 90)
(descr "Through hole straight pin header, 1x06, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x06 2.54mm single row")
(path /60D73F25)
(fp_text reference J1 (at 0 -2.33 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x06 (at 0 15.03 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 6.35) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 13.97) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 13.97) (end -1.27 13.97) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 13.97) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 14.03) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 14.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 14.5) (end 1.8 14.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 14.5) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 3 "Net-(J1-Pad6)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 "Net-(J1-Pad5)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 55 ~CDAC))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 5 "Net-(J1-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 6 "Net-(J1-Pad2)"))
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 7 "Net-(J1-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x06_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 60C6DA60)
(at 154.94 81.28)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3*2mm^2, Capacitor")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3mm width 2mm Capacitor")
(path /60C64C51)
(fp_text reference C1 (at 1.25 -2.25) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 0.1uF (at 1.25 2.25) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0) (layer F.Fab)
(effects (font (size 0.6 0.6) (thickness 0.09)))
)
(fp_line (start -0.25 -1) (end -0.25 1) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 1) (end 2.75 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 1) (end 2.75 -1) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 -1) (end -0.25 -1) (layer F.Fab) (width 0.1))
(fp_line (start -0.37 -1.12) (end 2.87 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -0.37 1.12) (end 2.87 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -0.37 -1.12) (end -0.37 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start -0.37 1.055) (end -0.37 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.87 -1.12) (end 2.87 -1.055) (layer F.SilkS) (width 0.12))
(fp_line (start 2.87 1.055) (end 2.87 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 3.55 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.25) (end 3.55 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(pad 2 thru_hole circle (at 2.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 VDD))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W2.0mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(gr_text "Reversed by tomse 2021\nhttps://retro-commodore.eu\n" (at 163.195 81.28 90) (layer F.Cu)
(effects (font (size 1.3 1.3) (thickness 0.15)))
)
(gr_text "AmiTech, DK\nMaxiMem\n" (at 135.255 80.01 90) (layer B.Cu)
(effects (font (size 1.5 1.5) (thickness 0.2)) (justify mirror))
)
(gr_text "GARY\nadapter" (at 134.62 118.745 90) (layer B.Cu)
(effects (font (size 1.5 1.5) (thickness 0.2)) (justify mirror))
)
(gr_arc (start 165.1 129.54) (end 165.1 130.81) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_arc (start 121.92 129.54) (end 120.65 129.54) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_arc (start 121.92 67.945) (end 121.92 66.675) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_arc (start 165.1 67.945) (end 166.37 67.945) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_line (start 165.1 66.675) (end 121.92 66.675) (layer Edge.Cuts) (width 0.05) (tstamp 60C6EB00))
(gr_line (start 166.37 129.54) (end 166.37 67.945) (layer Edge.Cuts) (width 0.05))
(gr_line (start 121.92 130.81) (end 165.1 130.81) (layer Edge.Cuts) (width 0.05))
(gr_line (start 120.65 67.945) (end 120.65 129.54) (layer Edge.Cuts) (width 0.05))
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(segment (start 137.16 94.615) (end 137.16 102.235) (width 0.25) (layer B.Cu) (net 14))
(segment (start 137.16 102.235) (end 137.795 102.87) (width 0.25) (layer B.Cu) (net 14))
(segment (start 137.795 93.98) (end 137.16 94.615) (width 0.25) (layer B.Cu) (net 14))
(segment (start 146.05 93.98) (end 137.795 93.98) (width 0.25) (layer B.Cu) (net 14))
(segment (start 147.32 95.25) (end 146.05 93.98) (width 0.25) (layer B.Cu) (net 14))
(segment (start 152.4 90.17) (end 160.02 90.17) (width 0.25) (layer B.Cu) (net 15))
(segment (start 147.955 92.71) (end 147.32 92.71) (width 0.25) (layer B.Cu) (net 15))
(segment (start 150.495 90.17) (end 147.955 92.71) (width 0.25) (layer B.Cu) (net 15))
(segment (start 152.4 90.17) (end 150.495 90.17) (width 0.25) (layer B.Cu) (net 15))
(segment (start 143.51 72.39) (end 139.7 72.39) (width 0.25) (layer B.Cu) (net 16))
(segment (start 139.7 74.93) (end 143.51 74.93) (width 0.25) (layer B.Cu) (net 17))
(segment (start 124.46 123.19) (end 128.27 123.19) (width 0.25) (layer B.Cu) (net 18))
(segment (start 143.51 77.47) (end 139.7 77.47) (width 0.25) (layer B.Cu) (net 19))
(segment (start 128.27 120.65) (end 124.46 120.65) (width 0.25) (layer B.Cu) (net 20))
(segment (start 139.7 80.01) (end 143.51 80.01) (width 0.25) (layer B.Cu) (net 21))
(segment (start 143.51 82.55) (end 139.7 82.55) (width 0.25) (layer B.Cu) (net 22))
(segment (start 128.27 115.57) (end 124.46 115.57) (width 0.25) (layer B.Cu) (net 23))
(segment (start 139.7 85.09) (end 143.51 85.09) (width 0.25) (layer B.Cu) (net 24))
(segment (start 124.46 113.03) (end 128.27 113.03) (width 0.25) (layer B.Cu) (net 25))
(segment (start 143.51 87.63) (end 139.7 87.63) (width 0.25) (layer B.Cu) (net 26))
(segment (start 128.27 110.49) (end 124.46 110.49) (width 0.25) (layer B.Cu) (net 27))
(segment (start 124.46 107.95) (end 128.27 107.95) (width 0.25) (layer B.Cu) (net 29))
(segment (start 143.51 92.71) (end 139.7 92.71) (width 0.25) (layer B.Cu) (net 30))
(segment (start 152.4 92.71) (end 149.86 92.71) (width 0.25) (layer B.Cu) (net 30))
(segment (start 149.86 92.71) (end 148.59 93.98) (width 0.25) (layer B.Cu) (net 30))
(segment (start 143.51 92.71) (end 146.05 92.71) (width 0.25) (layer B.Cu) (net 30))
(segment (start 146.05 92.71) (end 147.32 93.98) (width 0.25) (layer B.Cu) (net 30))
(segment (start 147.32 93.98) (end 148.59 93.98) (width 0.25) (layer B.Cu) (net 30))
(segment (start 139.7 95.25) (end 143.51 95.25) (width 0.25) (layer B.Cu) (net 31))
(segment (start 143.51 95.25) (end 146.05 95.25) (width 0.25) (layer B.Cu) (net 31))
(segment (start 146.05 95.25) (end 147.32 96.52) (width 0.25) (layer B.Cu) (net 31))
(segment (start 150.495 95.25) (end 152.4 95.25) (width 0.25) (layer B.Cu) (net 31))
(segment (start 149.225 96.52) (end 150.495 95.25) (width 0.25) (layer B.Cu) (net 31))
(segment (start 147.32 96.52) (end 149.225 96.52) (width 0.25) (layer B.Cu) (net 31))
(segment (start 124.46 102.87) (end 128.27 102.87) (width 0.25) (layer B.Cu) (net 32))
(segment (start 143.51 97.79) (end 139.7 97.79) (width 0.25) (layer B.Cu) (net 33))
(segment (start 152.4 97.79) (end 150.495 97.79) (width 0.25) (layer B.Cu) (net 33))
(segment (start 150.495 97.79) (end 149.225 99.06) (width 0.25) (layer B.Cu) (net 33))
(segment (start 147.32 99.06) (end 146.05 97.79) (width 0.25) (layer B.Cu) (net 33))
(segment (start 146.05 97.79) (end 143.51 97.79) (width 0.25) (layer B.Cu) (net 33))
(segment (start 147.32 99.06) (end 149.225 99.06) (width 0.25) (layer B.Cu) (net 33))
(segment (start 128.27 100.33) (end 124.46 100.33) (width 0.25) (layer B.Cu) (net 34))
(segment (start 152.4 100.33) (end 150.495 100.33) (width 0.25) (layer B.Cu) (net 35))
(segment (start 150.495 100.33) (end 149.225 101.6) (width 0.25) (layer B.Cu) (net 35))
(segment (start 147.32 101.6) (end 146.05 100.33) (width 0.25) (layer B.Cu) (net 35))
(segment (start 146.05 100.33) (end 143.51 100.33) (width 0.25) (layer B.Cu) (net 35))
(segment (start 147.32 101.6) (end 149.225 101.6) (width 0.25) (layer B.Cu) (net 35))
(segment (start 124.46 97.79) (end 128.27 97.79) (width 0.25) (layer B.Cu) (net 36))
(segment (start 152.4 102.87) (end 150.495 102.87) (width 0.25) (layer B.Cu) (net 37))
(segment (start 150.495 102.87) (end 149.225 104.14) (width 0.25) (layer B.Cu) (net 37))
(segment (start 147.32 104.14) (end 146.05 102.87) (width 0.25) (layer B.Cu) (net 37))
(segment (start 146.05 102.87) (end 143.51 102.87) (width 0.25) (layer B.Cu) (net 37))
(segment (start 147.32 104.14) (end 149.225 104.14) (width 0.25) (layer B.Cu) (net 37))
(segment (start 128.27 95.25) (end 124.46 95.25) (width 0.25) (layer B.Cu) (net 38))
(segment (start 143.51 105.41) (end 139.7 105.41) (width 0.25) (layer B.Cu) (net 39))
(segment (start 152.4 105.41) (end 150.495 105.41) (width 0.25) (layer B.Cu) (net 39))
(segment (start 150.495 105.41) (end 149.225 106.68) (width 0.25) (layer B.Cu) (net 39))
(segment (start 147.32 106.68) (end 146.05 105.41) (width 0.25) (layer B.Cu) (net 39))
(segment (start 146.05 105.41) (end 143.51 105.41) (width 0.25) (layer B.Cu) (net 39))
(segment (start 147.32 106.68) (end 149.225 106.68) (width 0.25) (layer B.Cu) (net 39))
(segment (start 124.46 92.71) (end 128.27 92.71) (width 0.25) (layer B.Cu) (net 40))
(segment (start 139.7 107.95) (end 143.51 107.95) (width 0.25) (layer B.Cu) (net 41))
(segment (start 124.46 90.17) (end 128.27 90.17) (width 0.25) (layer B.Cu) (net 42))
(segment (start 143.51 110.49) (end 139.7 110.49) (width 0.25) (layer B.Cu) (net 43))
(segment (start 128.27 87.63) (end 124.46 87.63) (width 0.25) (layer B.Cu) (net 44))
(segment (start 139.7 113.03) (end 143.51 113.03) (width 0.25) (layer B.Cu) (net 45))
(segment (start 124.46 85.09) (end 128.27 85.09) (width 0.25) (layer B.Cu) (net 46))
(segment (start 143.51 115.57) (end 139.7 115.57) (width 0.25) (layer B.Cu) (net 47))
(segment (start 128.27 82.55) (end 124.46 82.55) (width 0.25) (layer B.Cu) (net 48))
(segment (start 139.7 118.11) (end 143.51 118.11) (width 0.25) (layer B.Cu) (net 49))
(segment (start 124.46 80.01) (end 128.27 80.01) (width 0.25) (layer B.Cu) (net 50))
(segment (start 143.51 120.65) (end 139.7 120.65) (width 0.25) (layer B.Cu) (net 51))
(segment (start 128.27 77.47) (end 124.46 77.47) (width 0.25) (layer B.Cu) (net 52))
(segment (start 139.7 123.19) (end 143.51 123.19) (width 0.25) (layer B.Cu) (net 53))
(segment (start 124.46 74.93) (end 128.27 74.93) (width 0.25) (layer B.Cu) (net 54))
(segment (start 143.51 125.73) (end 139.7 125.73) (width 0.25) (layer B.Cu) (net 55))
(segment (start 140.97 125.73) (end 156.21 125.73) (width 0.25) (layer B.Cu) (net 55))
(segment (start 157.48 124.46) (end 157.48 118.11) (width 0.25) (layer B.Cu) (net 55))
(segment (start 156.21 125.73) (end 157.48 124.46) (width 0.25) (layer B.Cu) (net 55))
(segment (start 128.27 72.39) (end 124.46 72.39) (width 0.25) (layer B.Cu) (net 56))
(segment (start 139.7 128.27) (end 143.51 128.27) (width 0.25) (layer B.Cu) (net 57))
(segment (start 124.46 69.85) (end 128.27 69.85) (width 0.25) (layer B.Cu) (net 58))
)

411
AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter.net Normal file
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@ -0,0 +1,411 @@
(export (version D)
(design
(source D:\CloudDrives\NextCloud\tomses-projects\AmiTech-MaxiMem-Gary-Adapter\AmiTech-MaxiMem-Gary-Adapter\AmiTech-MaxiMem-Gary-Adapter.sch)
(date "06/13/21 21:11:16")
(tool "Eeschema (5.1.10)-1")
(sheet (number 1) (name /) (tstamps /)
(title_block
(title "MaxiMem Gary Adapter")
(company AmiTech)
(rev 1.0)
(date 2021-06-07)
(source AmiTech-MaxiMem-Gary-Adapter.sch)
(comment (number 1) (value ""))
(comment (number 2) (value ""))
(comment (number 3) (value "by Tomse 2021"))
(comment (number 4) (value https://retro-commodore.eu)))))
(components
(comp (ref J2)
(value Conn_01x05)
(footprint Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical)
(datasheet ~)
(libsource (lib Connector_Generic) (part Conn_01x05) (description "Generic connector, single row, 01x05, script generated (kicad-library-utils/schlib/autogen/connector/)"))
(sheetpath (names /) (tstamps /))
(tstamp 60C63EE3))
(comp (ref C1)
(value 0.1uF)
(footprint Capacitor_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm)
(datasheet ~)
(libsource (lib Device) (part C) (description "Unpolarized capacitor"))
(sheetpath (names /) (tstamps /))
(tstamp 60C64C51))
(comp (ref U3)
(value 18v8)
(footprint Package_DIP:DIP-20_W7.62mm_LongPads)
(libsource (lib 18v8) (part 18v8) (description ""))
(sheetpath (names /) (tstamps /))
(tstamp 60C83DE9))
(comp (ref U2)
(value GARY)
(footprint Package_DIP:DIP-48_W15.24mm_LongPads)
(libsource (lib amiga-chips) (part GARY) (description "Gary custom chip found in Amiga A500 A2000"))
(sheetpath (names /) (tstamps /))
(tstamp 60C88597))
(comp (ref U1)
(value Socket)
(footprint Package_DIP:DIP-48_W15.24mm_LongPads)
(libsource (lib amiga-chips) (part GARY) (description "Gary custom chip found in Amiga A500 A2000"))
(sheetpath (names /) (tstamps /))
(tstamp 60C91C09))
(comp (ref RN1)
(value 10k)
(footprint Resistor_THT:R_Array_SIP9)
(datasheet http://www.vishay.com/docs/31509/csc.pdf)
(libsource (lib Device) (part R_Network08) (description "8 resistor network, star topology, bussed resistors, small symbol"))
(sheetpath (names /) (tstamps /))
(tstamp 60C861BD))
(comp (ref J1)
(value Conn_01x06)
(footprint Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical)
(datasheet ~)
(libsource (lib Connector_Generic) (part Conn_01x06) (description "Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)"))
(sheetpath (names /) (tstamps /))
(tstamp 60D73F25)))
(libparts
(libpart (lib 18v8) (part 18v8)
(fields
(field (name Reference) U)
(field (name Value) 18v8))
(pins
(pin (num 1) (name I/CLK) (type input))
(pin (num 2) (name I) (type input))
(pin (num 3) (name I) (type input))
(pin (num 4) (name I) (type input))
(pin (num 5) (name I) (type input))
(pin (num 6) (name I) (type input))
(pin (num 7) (name I) (type input))
(pin (num 8) (name I) (type input))
(pin (num 9) (name I) (type input))
(pin (num 10) (name GND) (type input))
(pin (num 11) (name I) (type input))
(pin (num 12) (name I/O) (type BiDi))
(pin (num 13) (name I/O) (type BiDi))
(pin (num 14) (name I/O) (type BiDi))
(pin (num 15) (name I/O) (type BiDi))
(pin (num 16) (name I/O) (type BiDi))
(pin (num 17) (name I/O) (type BiDi))
(pin (num 18) (name I/O) (type BiDi))
(pin (num 19) (name I/O) (type BiDi))
(pin (num 20) (name VCC) (type power_in))))
(libpart (lib Connector_Generic) (part Conn_01x05)
(description "Generic connector, single row, 01x05, script generated (kicad-library-utils/schlib/autogen/connector/)")
(docs ~)
(footprints
(fp Connector*:*_1x??_*))
(fields
(field (name Reference) J)
(field (name Value) Conn_01x05))
(pins
(pin (num 1) (name Pin_1) (type passive))
(pin (num 2) (name Pin_2) (type passive))
(pin (num 3) (name Pin_3) (type passive))
(pin (num 4) (name Pin_4) (type passive))
(pin (num 5) (name Pin_5) (type passive))))
(libpart (lib Connector_Generic) (part Conn_01x06)
(description "Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)")
(docs ~)
(footprints
(fp Connector*:*_1x??_*))
(fields
(field (name Reference) J)
(field (name Value) Conn_01x06))
(pins
(pin (num 1) (name Pin_1) (type passive))
(pin (num 2) (name Pin_2) (type passive))
(pin (num 3) (name Pin_3) (type passive))
(pin (num 4) (name Pin_4) (type passive))
(pin (num 5) (name Pin_5) (type passive))
(pin (num 6) (name Pin_6) (type passive))))
(libpart (lib Device) (part C)
(description "Unpolarized capacitor")
(docs ~)
(footprints
(fp C_*))
(fields
(field (name Reference) C)
(field (name Value) C))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib Device) (part R_Network08)
(description "8 resistor network, star topology, bussed resistors, small symbol")
(docs http://www.vishay.com/docs/31509/csc.pdf)
(footprints
(fp R?Array?SIP*))
(fields
(field (name Reference) RN)
(field (name Value) R_Network08)
(field (name Footprint) Resistor_THT:R_Array_SIP9))
(pins
(pin (num 1) (name common) (type passive))
(pin (num 2) (name R1) (type passive))
(pin (num 3) (name R2) (type passive))
(pin (num 4) (name R3) (type passive))
(pin (num 5) (name R4) (type passive))
(pin (num 6) (name R5) (type passive))
(pin (num 7) (name R6) (type passive))
(pin (num 8) (name R7) (type passive))
(pin (num 9) (name R8) (type passive))))
(libpart (lib amiga-chips) (part GARY)
(description "Gary custom chip found in Amiga A500 A2000")
(fields
(field (name Reference) U)
(field (name Value) GARY))
(pins
(pin (num 1) (name VSS) (type power_in))
(pin (num 2) (name _VPA) (type output))
(pin (num 3) (name _CDR) (type output))
(pin (num 4) (name _CDW) (type output))
(pin (num 5) (name _KRES) (type input))
(pin (num 6) (name VDD) (type power_in))
(pin (num 7) (name _MTR) (type input))
(pin (num 8) (name _DKWD) (type input))
(pin (num 9) (name _DKWE) (type input))
(pin (num 10) (name _LDS) (type input))
(pin (num 11) (name _UDS) (type input))
(pin (num 12) (name R/W) (type input))
(pin (num 13) (name _AS) (type input))
(pin (num 14) (name _BGACK) (type input))
(pin (num 15) (name _DBR) (type input))
(pin (num 16) (name _SEL0) (type input))
(pin (num 17) (name VDD) (type power_in))
(pin (num 18) (name _RGAE) (type output))
(pin (num 19) (name _BLS) (type output))
(pin (num 20) (name _RAME) (type output))
(pin (num 21) (name _ROME) (type output))
(pin (num 22) (name _RTCR) (type output))
(pin (num 23) (name _RTCW) (type output))
(pin (num 24) (name VSS) (type power_in))
(pin (num 25) (name _LATCH) (type input))
(pin (num 26) (name _CDAC) (type output))
(pin (num 27) (name CCKQ) (type input))
(pin (num 28) (name CCK) (type input))
(pin (num 29) (name _NOVR) (type input))
(pin (num 30) (name OVL) (type input))
(pin (num 31) (name XRDY) (type input))
(pin (num 32) (name _NEXP) (type input))
(pin (num 33) (name A17) (type input))
(pin (num 34) (name A18) (type input))
(pin (num 35) (name A19) (type input))
(pin (num 36) (name A20) (type input))
(pin (num 37) (name A21) (type input))
(pin (num 38) (name A22) (type input))
(pin (num 39) (name A23) (type input))
(pin (num 40) (name N/C) (type NotConnected))
(pin (num 41) (name _RST) (type output))
(pin (num 42) (name _HLT) (type output))
(pin (num 43) (name _DTACK) (type output))
(pin (num 44) (name DKWEB) (type output))
(pin (num 45) (name DKWDB) (type output))
(pin (num 46) (name MTR0D) (type output))
(pin (num 47) (name MTRXD) (type output))
(pin (num 48) (name VDD) (type power_in)))))
(libraries
(library (logical 18v8)
(uri D:\CloudDrives\NextCloud\tomses-projects\AmiTech-Maximem\18v8.lib))
(library (logical Connector_Generic)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library/Connector_Generic.lib"))
(library (logical Device)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library/Device.lib"))
(library (logical amiga-chips)
(uri D:\CloudDrives\NextCloud\tomses-projects\KiCAD-Libraries\Amiga\LibraryFiles\amiga-chips.lib)))
(nets
(net (code 1) (name "Net-(RN1-Pad4)")
(node (ref U2) (pin 35))
(node (ref RN1) (pin 4))
(node (ref U3) (pin 18)))
(net (code 2) (name "Net-(J1-Pad1)")
(node (ref U3) (pin 1))
(node (ref RN1) (pin 2))
(node (ref J1) (pin 1)))
(net (code 3) (name "Net-(RN1-Pad3)")
(node (ref U3) (pin 2))
(node (ref U3) (pin 19))
(node (ref RN1) (pin 3)))
(net (code 4) (name "Net-(RN1-Pad1)")
(node (ref RN1) (pin 1)))
(net (code 5) (name "Net-(J1-Pad3)")
(node (ref J1) (pin 3))
(node (ref U3) (pin 11))
(node (ref RN1) (pin 8)))
(net (code 6) (name "Net-(J1-Pad2)")
(node (ref J1) (pin 2))
(node (ref U3) (pin 9))
(node (ref RN1) (pin 9)))
(net (code 7) (name ~LATCH)
(node (ref U2) (pin 25))
(node (ref U1) (pin 25)))
(net (code 8) (name ~CDAC)
(node (ref U2) (pin 26))
(node (ref U1) (pin 26)))
(net (code 9) (name CCKQ)
(node (ref U1) (pin 27))
(node (ref U2) (pin 27)))
(net (code 10) (name MTRXD)
(node (ref U2) (pin 47))
(node (ref U1) (pin 47)))
(net (code 11) (name VDD)
(node (ref U3) (pin 20))
(node (ref C1) (pin 1))
(node (ref U2) (pin 48))
(node (ref U1) (pin 48)))
(net (code 12) (name ~DTACK)
(node (ref U1) (pin 43))
(node (ref U2) (pin 43)))
(net (code 13) (name MTROD)
(node (ref U2) (pin 46))
(node (ref U1) (pin 46)))
(net (code 14) (name DKWDB)
(node (ref U1) (pin 45))
(node (ref U2) (pin 45)))
(net (code 15) (name DKWEB)
(node (ref U1) (pin 44))
(node (ref U2) (pin 44)))
(net (code 16) (name ~HLT)
(node (ref U2) (pin 42))
(node (ref U1) (pin 42)))
(net (code 17) (name ~RST)
(node (ref U1) (pin 41))
(node (ref U2) (pin 41)))
(net (code 18) (name A17)
(node (ref U2) (pin 33))
(node (ref U1) (pin 33)))
(net (code 19) (name ~NEXP)
(node (ref U1) (pin 32))
(node (ref U2) (pin 32)))
(net (code 20) (name XRDY)
(node (ref U1) (pin 31))
(node (ref U2) (pin 31)))
(net (code 21) (name OVL)
(node (ref U2) (pin 30))
(node (ref U1) (pin 30)))
(net (code 22) (name ~NOVR)
(node (ref U1) (pin 29))
(node (ref U2) (pin 29)))
(net (code 23) (name CCK)
(node (ref U2) (pin 28))
(node (ref U1) (pin 28)))
(net (code 24) (name "Net-(J1-Pad4)")
(node (ref U1) (pin 23))
(node (ref U2) (pin 23))
(node (ref J1) (pin 4)))
(net (code 25) (name A18)
(node (ref U3) (pin 8))
(node (ref U2) (pin 34))
(node (ref U1) (pin 34)))
(net (code 26) (name /A19)
(node (ref U1) (pin 35))
(node (ref U3) (pin 7)))
(net (code 27) (name /A20)
(node (ref U1) (pin 36))
(node (ref U3) (pin 6)))
(net (code 28) (name "Net-(J2-Pad2)")
(node (ref J2) (pin 2))
(node (ref U3) (pin 13))
(node (ref RN1) (pin 6)))
(net (code 29) (name "Net-(J2-Pad1)")
(node (ref RN1) (pin 7))
(node (ref J2) (pin 1))
(node (ref U3) (pin 12)))
(net (code 30) (name A23)
(node (ref U3) (pin 3))
(node (ref U2) (pin 39))
(node (ref U1) (pin 39)))
(net (code 31) (name A21)
(node (ref U3) (pin 5))
(node (ref U1) (pin 37))
(node (ref U2) (pin 37)))
(net (code 32) (name "Net-(J2-Pad5)")
(node (ref J2) (pin 5))
(node (ref U3) (pin 16)))
(net (code 33) (name "Net-(J2-Pad4)")
(node (ref J2) (pin 4))
(node (ref U3) (pin 15)))
(net (code 34) (name "Net-(J2-Pad3)")
(node (ref J2) (pin 3))
(node (ref U3) (pin 14)))
(net (code 35) (name A22)
(node (ref U2) (pin 38))
(node (ref U3) (pin 4))
(node (ref U1) (pin 38)))
(net (code 36) (name "Net-(RN1-Pad5)")
(node (ref U2) (pin 36))
(node (ref RN1) (pin 5))
(node (ref U3) (pin 17)))
(net (code 37) (name "Net-(U1-Pad18)")
(node (ref U1) (pin 18))
(node (ref U2) (pin 18)))
(net (code 38) (name "Net-(U1-Pad17)")
(node (ref U2) (pin 17))
(node (ref U1) (pin 17)))
(net (code 39) (name "Net-(U1-Pad16)")
(node (ref U2) (pin 16))
(node (ref U1) (pin 16)))
(net (code 40) (name GND)
(node (ref U3) (pin 10))
(node (ref U2) (pin 24))
(node (ref U1) (pin 24))
(node (ref C1) (pin 2)))
(net (code 41) (name "Net-(U1-Pad40)")
(node (ref U1) (pin 40)))
(net (code 42) (name "Net-(U1-Pad19)")
(node (ref U1) (pin 19))
(node (ref U2) (pin 19)))
(net (code 43) (name "Net-(U1-Pad8)")
(node (ref U1) (pin 8))
(node (ref U2) (pin 8)))
(net (code 44) (name "Net-(U1-Pad22)")
(node (ref U2) (pin 22))
(node (ref U1) (pin 22)))
(net (code 45) (name "Net-(U1-Pad21)")
(node (ref U1) (pin 21))
(node (ref U2) (pin 21)))
(net (code 46) (name "Net-(U1-Pad11)")
(node (ref U1) (pin 11))
(node (ref U2) (pin 11)))
(net (code 47) (name "Net-(U2-Pad40)")
(node (ref U2) (pin 40)))
(net (code 48) (name "Net-(J1-Pad6)")
(node (ref J1) (pin 6))
(node (ref U1) (pin 20))
(node (ref U2) (pin 20)))
(net (code 49) (name "Net-(U1-Pad10)")
(node (ref U2) (pin 10))
(node (ref U1) (pin 10)))
(net (code 50) (name "Net-(U1-Pad9)")
(node (ref U2) (pin 9))
(node (ref U1) (pin 9)))
(net (code 51) (name "Net-(U1-Pad12)")
(node (ref U1) (pin 12))
(node (ref U2) (pin 12)))
(net (code 52) (name "Net-(U1-Pad7)")
(node (ref U1) (pin 7))
(node (ref U2) (pin 7)))
(net (code 53) (name "Net-(U1-Pad6)")
(node (ref U2) (pin 6))
(node (ref U1) (pin 6)))
(net (code 54) (name "Net-(U1-Pad5)")
(node (ref U1) (pin 5))
(node (ref U2) (pin 5)))
(net (code 55) (name "Net-(U1-Pad4)")
(node (ref U1) (pin 4))
(node (ref U2) (pin 4)))
(net (code 56) (name "Net-(U1-Pad3)")
(node (ref U1) (pin 3))
(node (ref U2) (pin 3)))
(net (code 57) (name "Net-(U1-Pad2)")
(node (ref U2) (pin 2))
(node (ref U1) (pin 2)))
(net (code 58) (name "Net-(U1-Pad1)")
(node (ref U2) (pin 1))
(node (ref U1) (pin 1)))
(net (code 59) (name "Net-(J1-Pad5)")
(node (ref U1) (pin 15))
(node (ref J1) (pin 5))
(node (ref U2) (pin 15)))
(net (code 60) (name "Net-(U1-Pad14)")
(node (ref U2) (pin 14))
(node (ref U1) (pin 14)))
(net (code 61) (name "Net-(U1-Pad13)")
(node (ref U1) (pin 13))
(node (ref U2) (pin 13)))))

259
AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter.pro Normal file
View File

@ -0,0 +1,259 @@
update=06/13/21 21:47:37
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=PWR
Clearance=0.2
TrackWidth=1
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

592
AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter.sch Normal file
View File

@ -0,0 +1,592 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title "MaxiMem Gary Adapter"
Date "2021-06-07"
Rev "1.0"
Comp "AmiTech"
Comment1 ""
Comment2 ""
Comment3 "by Tomse 2021"
Comment4 "https://retro-commodore.eu"
$EndDescr
$Comp
L Connector_Generic:Conn_01x05 J2
U 1 1 60C63EE3
P 4950 4300
F 0 "J2" H 5030 4342 50 0000 L CNN
F 1 "Conn_01x05" H 5030 4251 50 0000 L CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical" H 4950 4300 50 0001 C CNN
F 3 "~" H 4950 4300 50 0001 C CNN
1 4950 4300
1 0 0 1
$EndComp
$Comp
L Device:C C1
U 1 1 60C64C51
P 6600 5650
F 0 "C1" H 6715 5696 50 0000 L CNN
F 1 "0.1uF" H 6715 5605 50 0000 L CNN
F 2 "Capacitor_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm" H 6638 5500 50 0001 C CNN
F 3 "~" H 6600 5650 50 0001 C CNN
1 6600 5650
1 0 0 -1
$EndComp
$Comp
L 18v8:18v8 U3
U 1 1 60C83DE9
P 4150 4150
F 0 "U3" H 4150 4200 50 0000 C CNN
F 1 "18v8" H 4150 4300 50 0000 C CNN
F 2 "Package_DIP:DIP-20_W7.62mm_LongPads" H 4100 3650 50 0001 C CNN
F 3 "" H 4100 3650 50 0001 C CNN
1 4150 4150
1 0 0 -1
$EndComp
$Comp
L amiga-chips:GARY U2
U 1 1 60C88597
P 9200 3750
F 0 "U2" H 9200 5147 60 0000 C CNN
F 1 "GARY" H 9200 5041 60 0000 C CNN
F 2 "Package_DIP:DIP-48_W15.24mm_LongPads" H 9250 4050 60 0001 C CNN
F 3 "" H 9250 4050 60 0001 C CNN
1 9200 3750
1 0 0 -1
$EndComp
$Comp
L amiga-chips:GARY U1
U 1 1 60C91C09
P 7450 3750
F 0 "U1" H 7450 5147 60 0000 C CNN
F 1 "Socket" H 7450 5041 60 0000 C CNN
F 2 "Package_DIP:DIP-48_W15.24mm_LongPads" H 7500 4050 60 0001 C CNN
F 3 "" H 7500 4050 60 0001 C CNN
1 7450 3750
-1 0 0 -1
$EndComp
Wire Wire Line
8150 2600 8500 2600
Wire Wire Line
8500 2700 8150 2700
Wire Wire Line
8150 2800 8500 2800
Wire Wire Line
8500 2900 8150 2900
Wire Wire Line
8150 3000 8500 3000
Wire Wire Line
8500 3100 8150 3100
Wire Wire Line
8150 3200 8500 3200
Wire Wire Line
8500 3300 8150 3300
Wire Wire Line
8150 3400 8500 3400
Wire Wire Line
8500 3500 8150 3500
Wire Wire Line
8150 3600 8500 3600
Wire Wire Line
8500 3700 8150 3700
Wire Wire Line
8150 3800 8500 3800
Wire Wire Line
8500 3900 8150 3900
Wire Wire Line
8150 4000 8300 4000
Wire Wire Line
8500 4100 8150 4100
Wire Wire Line
8150 4200 8500 4200
Wire Wire Line
8500 4300 8150 4300
Wire Wire Line
8150 4400 8500 4400
Wire Wire Line
8500 4500 8400 4500
Wire Wire Line
8150 4600 8500 4600
Wire Wire Line
8500 4700 8150 4700
Wire Wire Line
8500 4900 8300 4900
Text GLabel 10000 2600 2 50 Input ~ 0
VDD
Text GLabel 10000 2700 2 50 Input ~ 0
MTRXD
Text GLabel 6650 2800 0 50 Input ~ 0
MTROD
Text GLabel 6650 2900 0 50 Input ~ 0
DKWDB
Text GLabel 6650 3000 0 50 Input ~ 0
DKWEB
Text GLabel 6350 3100 0 50 Input ~ 0
~DTACK
Text GLabel 6650 3200 0 50 Input ~ 0
~HLT
Text GLabel 6350 3300 0 50 Input ~ 0
~RST
Text GLabel 6650 4100 0 50 Input ~ 0
A17
Text GLabel 6350 4200 0 50 Input ~ 0
~NEXP
Text GLabel 6650 4300 0 50 Input ~ 0
XRDY
Text GLabel 6650 4400 0 50 Input ~ 0
OVL
Text GLabel 6350 4500 0 50 Input ~ 0
~NOVR
Text GLabel 6650 4600 0 50 Input ~ 0
CCK
Text GLabel 6650 4700 0 50 Input ~ 0
CCKQ
Text GLabel 6650 4900 0 50 Input ~ 0
~LATCH
Text GLabel 6650 2700 0 50 Input ~ 0
MTRXD
Text GLabel 6650 2600 0 50 Input ~ 0
VDD
Text GLabel 10000 2800 2 50 Input ~ 0
MTROD
Text GLabel 10000 2900 2 50 Input ~ 0
DKWDB
Text GLabel 10000 3000 2 50 Input ~ 0
DKWEB
Text GLabel 10400 3100 2 50 Input ~ 0
~DTACK
Text GLabel 10000 3200 2 50 Input ~ 0
~HLT
Text GLabel 10400 3300 2 50 Input ~ 0
~RST
Text GLabel 10000 3500 2 50 Input ~ 0
A23
Text GLabel 10000 3600 2 50 Input ~ 0
A22
Text GLabel 10000 3700 2 50 Input ~ 0
A21
Text GLabel 10000 4000 2 50 Input ~ 0
A18
Text GLabel 10000 4100 2 50 Input ~ 0
A17
Text GLabel 10400 4200 2 50 Input ~ 0
~NEXP
Text GLabel 10000 4300 2 50 Input ~ 0
XRDY
Text GLabel 10000 4400 2 50 Input ~ 0
OVL
Text GLabel 10400 4500 2 50 Input ~ 0
~NOVR
Text GLabel 10000 4600 2 50 Input ~ 0
CCK
Text GLabel 10000 4700 2 50 Input ~ 0
CCKQ
Text GLabel 10400 4800 2 50 Input ~ 0
~CDAC
Text GLabel 10000 4900 2 50 Input ~ 0
~LATCH
Wire Wire Line
9900 2600 10000 2600
Wire Wire Line
10000 2700 9900 2700
Wire Wire Line
9900 2800 10000 2800
Wire Wire Line
10000 2900 9900 2900
Wire Wire Line
9900 3000 10000 3000
Wire Wire Line
9900 3100 10400 3100
Wire Wire Line
10000 3200 9900 3200
Wire Wire Line
9900 3300 10400 3300
Wire Wire Line
10000 3500 9900 3500
Wire Wire Line
9900 3600 10000 3600
Wire Wire Line
10000 3700 9900 3700
Wire Wire Line
9900 4000 10000 4000
Wire Wire Line
10000 4100 9900 4100
Wire Wire Line
9900 4200 10400 4200
Wire Wire Line
10000 4300 9900 4300
Wire Wire Line
9900 4400 10000 4400
Wire Wire Line
9900 4500 10400 4500
Wire Wire Line
10000 4600 9900 4600
Wire Wire Line
9900 4700 10000 4700
Wire Wire Line
10400 4800 9900 4800
Wire Wire Line
10000 4900 9900 4900
Wire Wire Line
6650 4900 6750 4900
Wire Wire Line
6650 4700 6750 4700
Wire Wire Line
6750 4600 6650 4600
Wire Wire Line
6350 4500 6750 4500
Wire Wire Line
6750 4400 6650 4400
Wire Wire Line
6650 4300 6750 4300
Wire Wire Line
6350 4200 6750 4200
Wire Wire Line
6650 4100 6750 4100
Wire Wire Line
6350 3300 6750 3300
Wire Wire Line
6750 3200 6650 3200
Wire Wire Line
6350 3100 6750 3100
Wire Wire Line
6750 3000 6650 3000
Wire Wire Line
6650 2900 6750 2900
Wire Wire Line
6750 2800 6650 2800
Wire Wire Line
6650 2700 6750 2700
Wire Wire Line
6750 2600 6700 2600
Wire Wire Line
3750 3700 3550 3700
Wire Wire Line
3750 3800 3650 3800
Wire Wire Line
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$Comp
L power:GND #PWR03
U 1 1 60D535E9
P 4150 5000
F 0 "#PWR03" H 4150 4750 50 0001 C CNN
F 1 "GND" H 4155 4827 50 0000 C CNN
F 2 "" H 4150 5000 50 0001 C CNN
F 3 "" H 4150 5000 50 0001 C CNN
1 4150 5000
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR02
U 1 1 60D543CD
P 4150 3500
F 0 "#PWR02" H 4150 3350 50 0001 C CNN
F 1 "+5V" H 4250 3600 50 0000 C CNN
F 2 "" H 4150 3500 50 0001 C CNN
F 3 "" H 4150 3500 50 0001 C CNN
1 4150 3500
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR01
U 1 1 60D6B453
P 6700 2500
F 0 "#PWR01" H 6700 2350 50 0001 C CNN
F 1 "+5V" H 6800 2600 50 0000 C CNN
F 2 "" H 6700 2500 50 0001 C CNN
F 3 "" H 6700 2500 50 0001 C CNN
1 6700 2500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR04
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P 8300 5050
F 0 "#PWR04" H 8300 4800 50 0001 C CNN
F 1 "GND" H 8305 4877 50 0000 C CNN
F 2 "" H 8300 5050 50 0001 C CNN
F 3 "" H 8300 5050 50 0001 C CNN
1 8300 5050
1 0 0 -1
$EndComp
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
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P 5150 1350
F 0 "RN1" H 5538 1396 50 0000 L CNN
F 1 "10k" H 5538 1305 50 0000 L CNN
F 2 "Resistor_THT:R_Array_SIP9" V 5625 1350 50 0001 C CNN
F 3 "http://www.vishay.com/docs/31509/csc.pdf" H 5150 1350 50 0001 C CNN
1 5150 1350
1 0 0 -1
$EndComp
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Wire Wire Line
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Wire Wire Line
4000 1550 4000 2600
Connection ~ 4000 2600
Wire Wire Line
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Wire Wire Line
3650 2700 4850 2700
$Comp
L Connector_Generic:Conn_01x06 J1
U 1 1 60D73F25
P 4200 1350
F 0 "J1" V 4164 962 50 0000 R CNN
F 1 "Conn_01x06" V 4073 962 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical" H 4200 1350 50 0001 C CNN
F 3 "~" H 4200 1350 50 0001 C CNN
1 4200 1350
0 -1 -1 0
$EndComp
Wire Wire Line
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Connection ~ 4850 2700
Wire Wire Line
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Wire Wire Line
5350 2500 4200 2500
Wire Wire Line
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Connection ~ 5350 2500
Wire Wire Line
4850 2700 4850 3800
Wire Wire Line
3650 2700 3650 3800
Wire Wire Line
3550 2600 3550 3700
Wire Wire Line
5350 2500 5350 5450
Wire Wire Line
3750 3900 3450 3900
Wire Wire Line
3450 3900 3450 3300
Wire Wire Line
3450 3300 5450 3300
Wire Wire Line
5450 3300 5450 3500
Wire Wire Line
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Wire Wire Line
3750 4000 3350 4000
Wire Wire Line
3350 4000 3350 3200
Wire Wire Line
3350 3200 5550 3200
Wire Wire Line
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Wire Wire Line
5550 3600 6750 3600
Wire Wire Line
4550 4500 4700 4500
Wire Wire Line
4750 4400 4650 4400
Wire Wire Line
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Wire Wire Line
4750 4200 4550 4200
Wire Wire Line
4550 4100 4750 4100
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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A21
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Wire Wire Line
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Wire Wire Line
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Connection ~ 4700 4500
Wire Wire Line
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Wire Wire Line
5150 1550 5150 4750
Wire Wire Line
5150 4750 4650 4750
Wire Wire Line
4650 4750 4650 4400
Connection ~ 4650 4400
Wire Wire Line
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Wire Wire Line
4550 3900 4950 3900
Wire Wire Line
4950 3900 4950 2300
Wire Wire Line
9900 3900 10550 3900
Wire Wire Line
10550 3900 10550 2300
Wire Wire Line
10550 2300 4950 2300
Connection ~ 4950 2300
Wire Wire Line
4950 2300 4950 1550
Wire Wire Line
4550 4000 5050 4000
Wire Wire Line
5050 4000 5050 2200
Wire Wire Line
5050 2200 10650 2200
Wire Wire Line
10650 2200 10650 3800
Wire Wire Line
10650 3800 9900 3800
Connection ~ 5050 2200
Wire Wire Line
5050 2200 5050 1550
Wire Wire Line
3750 4500 2850 4500
Wire Wire Line
2850 4500 2850 2400
Wire Wire Line
2850 2400 4100 2400
Wire Wire Line
5450 1550 5450 2400
Wire Wire Line
5450 2400 4100 2400
Connection ~ 4100 2400
Wire Wire Line
4100 2400 4100 1550
Wire Wire Line
8300 5050 8300 4900
Connection ~ 8300 4900
Wire Wire Line
8300 4900 8150 4900
$Comp
L power:+5V #PWR05
U 1 1 60E775E6
P 6600 5400
F 0 "#PWR05" H 6600 5250 50 0001 C CNN
F 1 "+5V" H 6700 5500 50 0000 C CNN
F 2 "" H 6600 5400 50 0001 C CNN
F 3 "" H 6600 5400 50 0001 C CNN
1 6600 5400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR06
U 1 1 60E783AC
P 6600 5900
F 0 "#PWR06" H 6600 5650 50 0001 C CNN
F 1 "GND" H 6605 5727 50 0000 C CNN
F 2 "" H 6600 5900 50 0001 C CNN
F 3 "" H 6600 5900 50 0001 C CNN
1 6600 5900
1 0 0 -1
$EndComp
Wire Wire Line
6600 5500 6600 5400
Wire Wire Line
6600 5900 6600 5800
Wire Wire Line
6750 3800 5750 3800
Wire Wire Line
5750 3800 5750 3000
Wire Wire Line
5750 3000 3150 3000
Wire Wire Line
3150 3000 3150 4200
Wire Wire Line
3150 4200 3750 4200
Wire Wire Line
6750 3900 5850 3900
Wire Wire Line
5850 3900 5850 2900
Wire Wire Line
5850 2900 3050 2900
Wire Wire Line
3050 2900 3050 4300
Wire Wire Line
3050 4300 3750 4300
Wire Wire Line
5950 4000 5950 2800
Wire Wire Line
5950 2800 2950 2800
Wire Wire Line
2950 2800 2950 4400
Wire Wire Line
2950 4400 3750 4400
Wire Wire Line
5950 4000 6750 4000
Text Label 3500 4200 0 50 ~ 0
A20
Text Label 3500 4300 0 50 ~ 0
A19
Text Label 3500 4400 0 50 ~ 0
A18
Wire Wire Line
4300 2100 4300 1550
Wire Wire Line
8300 4000 8300 2000
Wire Wire Line
8300 2000 4400 2000
Wire Wire Line
4400 2000 4400 1550
Connection ~ 8300 4000
Wire Wire Line
8300 4000 8500 4000
Wire Wire Line
4500 1550 4500 1900
Wire Wire Line
4500 1900 8400 1900
Wire Wire Line
8400 1900 8400 4500
Connection ~ 8400 4500
Wire Wire Line
8400 4500 8150 4500
Wire Wire Line
6700 2600 6700 2500
Connection ~ 6700 2600
Wire Wire Line
6700 2600 6650 2600
Wire Wire Line
8150 4800 8500 4800
Wire Wire Line
6050 4800 6050 2100
Wire Wire Line
6050 4800 6750 4800
Wire Wire Line
4300 2100 6050 2100
Text Label 5800 2100 0 50 ~ 0
~CDAC
Wire Wire Line
4750 1150 4750 1050
$Comp
L power:+5V #PWR?
U 1 1 60FA4786
P 4750 1050
F 0 "#PWR?" H 4750 900 50 0001 C CNN
F 1 "+5V" H 4850 1150 50 0000 C CNN
F 2 "" H 4750 1050 50 0001 C CNN
F 3 "" H 4750 1050 50 0001 C CNN
1 4750 1050
1 0 0 -1
$EndComp
$EndSCHEMATC

596
AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter.sch-bak Normal file
View File

@ -0,0 +1,596 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title "MaxiMem Gary Adapter"
Date "2021-06-07"
Rev "1.0"
Comp "AmiTech"
Comment1 ""
Comment2 ""
Comment3 "by Tomse 2021"
Comment4 "https://retro-commodore.eu"
$EndDescr
$Comp
L Connector_Generic:Conn_01x05 J2
U 1 1 60C63EE3
P 4950 4300
F 0 "J2" H 5030 4342 50 0000 L CNN
F 1 "Conn_01x05" H 5030 4251 50 0000 L CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical" H 4950 4300 50 0001 C CNN
F 3 "~" H 4950 4300 50 0001 C CNN
1 4950 4300
1 0 0 1
$EndComp
$Comp
L Device:C C1
U 1 1 60C64C51
P 6600 5650
F 0 "C1" H 6715 5696 50 0000 L CNN
F 1 "0.1uF" H 6715 5605 50 0000 L CNN
F 2 "Capacitor_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm" H 6638 5500 50 0001 C CNN
F 3 "~" H 6600 5650 50 0001 C CNN
1 6600 5650
1 0 0 -1
$EndComp
$Comp
L 18v8:18v8 U3
U 1 1 60C83DE9
P 4150 4150
F 0 "U3" H 4150 4200 50 0000 C CNN
F 1 "18v8" H 4150 4300 50 0000 C CNN
F 2 "Package_DIP:DIP-20_W7.62mm_LongPads" H 4100 3650 50 0001 C CNN
F 3 "" H 4100 3650 50 0001 C CNN
1 4150 4150
1 0 0 -1
$EndComp
$Comp
L amiga-chips:GARY U2
U 1 1 60C88597
P 9200 3750
F 0 "U2" H 9200 5147 60 0000 C CNN
F 1 "GARY" H 9200 5041 60 0000 C CNN
F 2 "Package_DIP:DIP-48_W15.24mm_LongPads" H 9250 4050 60 0001 C CNN
F 3 "" H 9250 4050 60 0001 C CNN
1 9200 3750
1 0 0 -1
$EndComp
$Comp
L amiga-chips:GARY U1
U 1 1 60C91C09
P 7450 3750
F 0 "U1" H 7450 5147 60 0000 C CNN
F 1 "Socket" H 7450 5041 60 0000 C CNN
F 2 "Package_DIP:DIP-48_W15.24mm_LongPads" H 7500 4050 60 0001 C CNN
F 3 "" H 7500 4050 60 0001 C CNN
1 7450 3750
-1 0 0 -1
$EndComp
Wire Wire Line
8150 2600 8500 2600
Wire Wire Line
8500 2700 8150 2700
Wire Wire Line
8150 2800 8500 2800
Wire Wire Line
8500 2900 8150 2900
Wire Wire Line
8150 3000 8500 3000
Wire Wire Line
8500 3100 8150 3100
Wire Wire Line
8150 3200 8500 3200
Wire Wire Line
8500 3300 8150 3300
Wire Wire Line
8150 3400 8500 3400
Wire Wire Line
8500 3500 8150 3500
Wire Wire Line
8150 3600 8500 3600
Wire Wire Line
8500 3700 8150 3700
Wire Wire Line
8150 3800 8500 3800
Wire Wire Line
8500 3900 8150 3900
Wire Wire Line
8150 4000 8300 4000
Wire Wire Line
8500 4100 8150 4100
Wire Wire Line
8150 4200 8500 4200
Wire Wire Line
8500 4300 8150 4300
Wire Wire Line
8150 4400 8500 4400
Wire Wire Line
8500 4500 8400 4500
Wire Wire Line
8150 4600 8500 4600
Wire Wire Line
8500 4700 8150 4700
Wire Wire Line
8500 4900 8300 4900
Text GLabel 10000 2600 2 50 Input ~ 0
VDD
Text GLabel 10000 2700 2 50 Input ~ 0
MTRXD
Text GLabel 6650 2800 0 50 Input ~ 0
MTROD
Text GLabel 6650 2900 0 50 Input ~ 0
DKWDB
Text GLabel 6650 3000 0 50 Input ~ 0
DKWEB
Text GLabel 6350 3100 0 50 Input ~ 0
~DTACK
Text GLabel 6650 3200 0 50 Input ~ 0
~HLT
Text GLabel 6350 3300 0 50 Input ~ 0
~RST
Text GLabel 6650 4100 0 50 Input ~ 0
A17
Text GLabel 6350 4200 0 50 Input ~ 0
~NEXP
Text GLabel 6650 4300 0 50 Input ~ 0
XRDY
Text GLabel 6650 4400 0 50 Input ~ 0
OVL
Text GLabel 6350 4500 0 50 Input ~ 0
~NOVR
Text GLabel 6650 4600 0 50 Input ~ 0
CCK
Text GLabel 6650 4700 0 50 Input ~ 0
CCKQ
Text GLabel 6650 4900 0 50 Input ~ 0
~LATCH
Text GLabel 6650 2700 0 50 Input ~ 0
MTRXD
Text GLabel 6650 2600 0 50 Input ~ 0
VDD
Text GLabel 10000 2800 2 50 Input ~ 0
MTROD
Text GLabel 10000 2900 2 50 Input ~ 0
DKWDB
Text GLabel 10000 3000 2 50 Input ~ 0
DKWEB
Text GLabel 10400 3100 2 50 Input ~ 0
~DTACK
Text GLabel 10000 3200 2 50 Input ~ 0
~HLT
Text GLabel 10400 3300 2 50 Input ~ 0
~RST
Text GLabel 10000 3500 2 50 Input ~ 0
A23
Text GLabel 10000 3600 2 50 Input ~ 0
A22
Text GLabel 10000 3700 2 50 Input ~ 0
A21
Text GLabel 10000 4000 2 50 Input ~ 0
A18
Text GLabel 10000 4100 2 50 Input ~ 0
A17
Text GLabel 10400 4200 2 50 Input ~ 0
~NEXP
Text GLabel 10000 4300 2 50 Input ~ 0
XRDY
Text GLabel 10000 4400 2 50 Input ~ 0
OVL
Text GLabel 10400 4500 2 50 Input ~ 0
~NOVR
Text GLabel 10000 4600 2 50 Input ~ 0
CCK
Text GLabel 10000 4700 2 50 Input ~ 0
CCKQ
Text GLabel 10400 4800 2 50 Input ~ 0
~CDAC
Text GLabel 10000 4900 2 50 Input ~ 0
~LATCH
Wire Wire Line
9900 2600 10000 2600
Wire Wire Line
10000 2700 9900 2700
Wire Wire Line
9900 2800 10000 2800
Wire Wire Line
10000 2900 9900 2900
Wire Wire Line
9900 3000 10000 3000
Wire Wire Line
9900 3100 10400 3100
Wire Wire Line
10000 3200 9900 3200
Wire Wire Line
9900 3300 10400 3300
Wire Wire Line
10000 3500 9900 3500
Wire Wire Line
9900 3600 10000 3600
Wire Wire Line
10000 3700 9900 3700
Wire Wire Line
9900 4000 10000 4000
Wire Wire Line
10000 4100 9900 4100
Wire Wire Line
9900 4200 10400 4200
Wire Wire Line
10000 4300 9900 4300
Wire Wire Line
9900 4400 10000 4400
Wire Wire Line
9900 4500 10400 4500
Wire Wire Line
10000 4600 9900 4600
Wire Wire Line
9900 4700 10000 4700
Wire Wire Line
10400 4800 9900 4800
Wire Wire Line
10000 4900 9900 4900
Wire Wire Line
6650 4900 6750 4900
Wire Wire Line
6650 4700 6750 4700
Wire Wire Line
6750 4600 6650 4600
Wire Wire Line
6350 4500 6750 4500
Wire Wire Line
6750 4400 6650 4400
Wire Wire Line
6650 4300 6750 4300
Wire Wire Line
6350 4200 6750 4200
Wire Wire Line
6650 4100 6750 4100
Wire Wire Line
6350 3300 6750 3300
Wire Wire Line
6750 3200 6650 3200
Wire Wire Line
6350 3100 6750 3100
Wire Wire Line
6750 3000 6650 3000
Wire Wire Line
6650 2900 6750 2900
Wire Wire Line
6750 2800 6650 2800
Wire Wire Line
6650 2700 6750 2700
Wire Wire Line
6750 2600 6700 2600
Wire Wire Line
3750 3700 3550 3700
Wire Wire Line
3750 3800 3650 3800
Wire Wire Line
4850 3800 4550 3800
$Comp
L power:GND #PWR03
U 1 1 60D535E9
P 4150 5000
F 0 "#PWR03" H 4150 4750 50 0001 C CNN
F 1 "GND" H 4155 4827 50 0000 C CNN
F 2 "" H 4150 5000 50 0001 C CNN
F 3 "" H 4150 5000 50 0001 C CNN
1 4150 5000
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR02
U 1 1 60D543CD
P 4150 3500
F 0 "#PWR02" H 4150 3350 50 0001 C CNN
F 1 "+5V" H 4250 3600 50 0000 C CNN
F 2 "" H 4150 3500 50 0001 C CNN
F 3 "" H 4150 3500 50 0001 C CNN
1 4150 3500
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR01
U 1 1 60D6B453
P 6700 2500
F 0 "#PWR01" H 6700 2350 50 0001 C CNN
F 1 "+5V" H 6800 2600 50 0000 C CNN
F 2 "" H 6700 2500 50 0001 C CNN
F 3 "" H 6700 2500 50 0001 C CNN
1 6700 2500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR04
U 1 1 60D6C277
P 8300 5050
F 0 "#PWR04" H 8300 4800 50 0001 C CNN
F 1 "GND" H 8305 4877 50 0000 C CNN
F 2 "" H 8300 5050 50 0001 C CNN
F 3 "" H 8300 5050 50 0001 C CNN
1 8300 5050
1 0 0 -1
$EndComp
Wire Wire Line
4150 5000 4150 4800
Wire Wire Line
5350 5450 3450 5450
Wire Wire Line
3450 5450 3450 4600
Wire Wire Line
3450 4600 3750 4600
$Comp
L Device:R_Network08 RN1
U 1 1 60C861BD
P 5150 1350
F 0 "RN1" H 5538 1396 50 0000 L CNN
F 1 "10k" H 5538 1305 50 0000 L CNN
F 2 "Resistor_THT:R_Array_SIP9" V 5625 1350 50 0001 C CNN
F 3 "http://www.vishay.com/docs/31509/csc.pdf" H 5150 1350 50 0001 C CNN
1 5150 1350
1 0 0 -1
$EndComp
Wire Wire Line
4750 1550 4750 2600
Wire Wire Line
3550 2600 4000 2600
Wire Wire Line
4000 1550 4000 2600
Connection ~ 4000 2600
Wire Wire Line
4000 2600 4750 2600
Wire Wire Line
3650 2700 4850 2700
$Comp
L Connector_Generic:Conn_01x06 J1
U 1 1 60D73F25
P 4200 1350
F 0 "J1" V 4164 962 50 0000 R CNN
F 1 "Conn_01x06" V 4073 962 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical" H 4200 1350 50 0001 C CNN
F 3 "~" H 4200 1350 50 0001 C CNN
1 4200 1350
0 -1 -1 0
$EndComp
Wire Wire Line
4850 1550 4850 2700
Connection ~ 4850 2700
Wire Wire Line
5350 1550 5350 2500
Wire Wire Line
5350 2500 4200 2500
Wire Wire Line
4200 2500 4200 1550
Connection ~ 5350 2500
Wire Wire Line
4850 2700 4850 3800
Wire Wire Line
3650 2700 3650 3800
Wire Wire Line
3550 2600 3550 3700
Wire Wire Line
5350 2500 5350 5450
Wire Wire Line
3750 3900 3450 3900
Wire Wire Line
3450 3900 3450 3300
Wire Wire Line
3450 3300 5450 3300
Wire Wire Line
5450 3300 5450 3500
Wire Wire Line
5450 3500 6750 3500
Wire Wire Line
3750 4000 3350 4000
Wire Wire Line
3350 4000 3350 3200
Wire Wire Line
3350 3200 5550 3200
Wire Wire Line
5550 3200 5550 3600
Wire Wire Line
5550 3600 6750 3600
Wire Wire Line
4550 4500 4700 4500
Wire Wire Line
4750 4400 4650 4400
Wire Wire Line
4550 4300 4750 4300
Wire Wire Line
4750 4200 4550 4200
Wire Wire Line
4550 4100 4750 4100
Wire Wire Line
6750 3700 5650 3700
Wire Wire Line
5650 3700 5650 3100
Wire Wire Line
5650 3100 3250 3100
Wire Wire Line
3250 3100 3250 4100
Wire Wire Line
3250 4100 3750 4100
Text Label 3500 4100 0 50 ~ 0
A21
Text Label 3500 4000 0 50 ~ 0
A22
Text Label 3500 3900 0 50 ~ 0
A23
Wire Wire Line
5250 1550 5250 4650
Wire Wire Line
5250 4650 4700 4650
Wire Wire Line
4700 4650 4700 4500
Connection ~ 4700 4500
Wire Wire Line
4700 4500 4750 4500
Wire Wire Line
5150 1550 5150 4750
Wire Wire Line
5150 4750 4650 4750
Wire Wire Line
4650 4750 4650 4400
Connection ~ 4650 4400
Wire Wire Line
4650 4400 4550 4400
Wire Wire Line
4550 3900 4950 3900
Wire Wire Line
4950 3900 4950 2300
Wire Wire Line
9900 3900 10550 3900
Wire Wire Line
10550 3900 10550 2300
Wire Wire Line
10550 2300 4950 2300
Connection ~ 4950 2300
Wire Wire Line
4950 2300 4950 1550
Wire Wire Line
4550 4000 5050 4000
Wire Wire Line
5050 4000 5050 2200
Wire Wire Line
5050 2200 10650 2200
Wire Wire Line
10650 2200 10650 3800
Wire Wire Line
10650 3800 9900 3800
Connection ~ 5050 2200
Wire Wire Line
5050 2200 5050 1550
Wire Wire Line
3750 4500 2850 4500
Wire Wire Line
2850 4500 2850 2400
Wire Wire Line
2850 2400 4100 2400
Wire Wire Line
5450 1550 5450 2400
Wire Wire Line
5450 2400 4100 2400
Connection ~ 4100 2400
Wire Wire Line
4100 2400 4100 1550
Wire Wire Line
8300 5050 8300 4900
Connection ~ 8300 4900
Wire Wire Line
8300 4900 8150 4900
$Comp
L power:+5V #PWR05
U 1 1 60E775E6
P 6600 5400
F 0 "#PWR05" H 6600 5250 50 0001 C CNN
F 1 "+5V" H 6700 5500 50 0000 C CNN
F 2 "" H 6600 5400 50 0001 C CNN
F 3 "" H 6600 5400 50 0001 C CNN
1 6600 5400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR06
U 1 1 60E783AC
P 6600 5900
F 0 "#PWR06" H 6600 5650 50 0001 C CNN
F 1 "GND" H 6605 5727 50 0000 C CNN
F 2 "" H 6600 5900 50 0001 C CNN
F 3 "" H 6600 5900 50 0001 C CNN
1 6600 5900
1 0 0 -1
$EndComp
Wire Wire Line
6600 5500 6600 5400
Wire Wire Line
6600 5900 6600 5800
Wire Wire Line
6750 3800 5750 3800
Wire Wire Line
5750 3800 5750 3000
Wire Wire Line
5750 3000 3150 3000
Wire Wire Line
3150 3000 3150 4200
Wire Wire Line
3150 4200 3750 4200
Wire Wire Line
6750 3900 5850 3900
Wire Wire Line
5850 3900 5850 2900
Wire Wire Line
5850 2900 3050 2900
Wire Wire Line
3050 2900 3050 4300
Wire Wire Line
3050 4300 3750 4300
Wire Wire Line
5950 4000 5950 2800
Wire Wire Line
5950 2800 2950 2800
Wire Wire Line
2950 2800 2950 4400
Wire Wire Line
2950 4400 3750 4400
Wire Wire Line
5950 4000 6750 4000
Text Label 3500 4200 0 50 ~ 0
A20
Text Label 3500 4300 0 50 ~ 0
A19
Text Label 3500 4400 0 50 ~ 0
A18
Wire Wire Line
4300 2100 4300 1550
Wire Wire Line
8300 4000 8300 2000
Wire Wire Line
8300 2000 4400 2000
Wire Wire Line
4400 2000 4400 1550
Connection ~ 8300 4000
Wire Wire Line
8300 4000 8500 4000
Wire Wire Line
4500 1550 4500 1900
Wire Wire Line
4500 1900 8400 1900
Wire Wire Line
8400 1900 8400 4500
Connection ~ 8400 4500
Wire Wire Line
8400 4500 8150 4500
Wire Wire Line
6700 2600 6700 2500
Connection ~ 6700 2600
Wire Wire Line
6700 2600 6650 2600
Wire Wire Line
8150 4800 8500 4800
Wire Wire Line
6050 4800 6050 2100
Wire Wire Line
6050 4800 6750 4800
Wire Wire Line
4300 2100 6050 2100
Text Label 5800 2100 0 50 ~ 0
~CDAC
$Comp
L power:GND #PWR?
U 1 1 60F99B30
P 4600 1100
F 0 "#PWR?" H 4600 850 50 0001 C CNN
F 1 "GND" H 4605 927 50 0000 C CNN
F 2 "" H 4600 1100 50 0001 C CNN
F 3 "" H 4600 1100 50 0001 C CNN
1 4600 1100
1 0 0 -1
$EndComp
Wire Wire Line
4750 1150 4750 1050
Wire Wire Line
4750 1050 4600 1050
Wire Wire Line
4600 1050 4600 1100
$EndSCHEMATC

86423
AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter/fp-info-cache Normal file
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4
AmiTech-MaxiMem-Gary-Adapter/AmiTech-MaxiMem-Gary-Adapter/sym-lib-table Normal file
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(sym_lib_table
(lib (name 18v8)(type Legacy)(uri D:/CloudDrives/NextCloud/tomses-projects/AmiTech-Maximem/18v8.lib)(options "")(descr ""))
(lib (name amiga-chips)(type Legacy)(uri D:/CloudDrives/NextCloud/tomses-projects/KiCAD-Libraries/Amiga/LibraryFiles/amiga-chips.lib)(options "")(descr ""))
)

BIN
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BIN
AmiTech-Maximem-CPU-Adapter/18CV8-25 datasheet.pdf Normal file
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3
AmiTech-Maximem-CPU-Adapter/18v8.bck Normal file
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@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

15
AmiTech-Maximem-CPU-Adapter/18v8.dcm Normal file
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@ -0,0 +1,15 @@
EESchema-DOCLIB Version 2.0
#
$CMP 64Pin_Socket
D 16/32-bit Microprocessor
K 68000 Microprocessor CPU
F https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf
$ENDCMP
#
$CMP 68010D_copy
D 16/32-bit Microprocessor
K 68000 Microprocessor CPU
F https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf
$ENDCMP
#
#End Doc Library

190
AmiTech-Maximem-CPU-Adapter/18v8.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 18v8
#
DEF 18v8 U 0 40 Y Y 1 F N
F0 "U" -100 650 50 H V C CNN
F1 "18v8" 0 750 50 H V C CNN
F2 "" -50 -500 50 H I C CNN
F3 "" -50 -500 50 H I C CNN
DRAW
S -300 550 300 -550 0 1 0 N
X I/CLK 1 -400 450 100 R 50 50 1 1 I
X GND 10 0 -650 100 U 50 50 1 1 I
X I 11 -400 -450 100 R 50 50 1 1 I
X I/O 12 400 -350 100 L 50 50 1 1 B
X I/O 13 400 -250 100 L 50 50 1 1 B
X I/O 14 400 -150 100 L 50 50 1 1 B
X I/O 15 400 -50 100 L 50 50 1 1 B
X I/O 16 400 50 100 L 50 50 1 1 B
X I/O 17 400 150 100 L 50 50 1 1 B
X I/O 18 400 250 100 L 50 50 1 1 B
X I/O 19 400 350 100 L 50 50 1 1 B
X I 2 -400 350 100 R 50 50 1 1 I
X VCC 20 0 650 100 D 50 50 1 1 W
X I 3 -400 250 100 R 50 50 1 1 I
X I 4 -400 150 100 R 50 50 1 1 I
X I 5 -400 50 100 R 50 50 1 1 I
X I 6 -400 -50 100 R 50 50 1 1 I
X I 7 -400 -150 100 R 50 50 1 1 I
X I 8 -400 -250 100 R 50 50 1 1 I
X I 9 -400 -350 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# 64Pin_Socket
#
DEF 64Pin_Socket U 0 30 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "64Pin_Socket" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 68010D_copy
DRAW
S -700 2250 700 -2250 0 1 10 f
X D4 1 1000 -600 300 L 50 50 1 1 B
X DTACK 10 -1000 -800 300 R 50 50 1 1 I I
X BG 11 -1000 1400 300 R 50 50 1 1 O I
X BGACK 12 -1000 1500 300 R 50 50 1 1 I I
X BR 13 -1000 1300 300 R 50 50 1 1 I I
X VCC 14 0 2400 150 D 50 50 1 1 W
X CLK 15 -1000 2200 300 R 50 50 1 1 I C
X GND 16 100 -2400 150 U 50 50 1 1 W
X HALT 17 -1000 -1200 300 R 50 50 1 1 B I
X RESET 18 -1000 -1300 300 R 50 50 1 1 B I
X VMA 19 -1000 500 300 R 50 50 1 1 O I
X D3 2 1000 -500 300 L 50 50 1 1 B
X E 20 -1000 400 300 R 50 50 1 1 O
X VPA 21 -1000 300 300 R 50 50 1 1 I I
X BERR 22 -1000 -600 300 R 50 50 1 1 I I
X IPL2 23 -1000 1700 300 R 50 50 1 1 I I
X IPL1 24 -1000 1800 300 R 50 50 1 1 I I
X IPL0 25 -1000 1900 300 R 50 50 1 1 I I
X FC2 26 -1000 800 300 R 50 50 1 1 O
X FC1 27 -1000 900 300 R 50 50 1 1 O
X FC0 28 -1000 1000 300 R 50 50 1 1 O
X A1 29 1000 2200 300 L 50 50 1 1 O
X D2 3 1000 -400 300 L 50 50 1 1 B
X A2 30 1000 2100 300 L 50 50 1 1 O
X A3 31 1000 2000 300 L 50 50 1 1 O
X A4 32 1000 1900 300 L 50 50 1 1 O
X A5 33 1000 1800 300 L 50 50 1 1 O
X A6 34 1000 1700 300 L 50 50 1 1 O
X A7 35 1000 1600 300 L 50 50 1 1 O
X A8 36 1000 1500 300 L 50 50 1 1 O
X A9 37 1000 1400 300 L 50 50 1 1 O
X A10 38 1000 1300 300 L 50 50 1 1 O
X A11 39 1000 1200 300 L 50 50 1 1 O
X D1 4 1000 -300 300 L 50 50 1 1 B
X A12 40 1000 1100 300 L 50 50 1 1 O
X A13 41 1000 1000 300 L 50 50 1 1 O
X A14 42 1000 900 300 L 50 50 1 1 O
X A15 43 1000 800 300 L 50 50 1 1 O
X A16 44 1000 700 300 L 50 50 1 1 O
X A17 45 1000 600 300 L 50 50 1 1 O
X A18 46 1000 500 300 L 50 50 1 1 O
X A19 47 1000 400 300 L 50 50 1 1 O
X A20 48 1000 300 300 L 50 50 1 1 O
X VCC 49 100 2400 150 D 50 50 1 1 W
X D0 5 1000 -200 300 L 50 50 1 1 B
X A21 50 1000 200 300 L 50 50 1 1 O
X A22 51 1000 100 300 L 50 50 1 1 O
X A23 52 1000 0 300 L 50 50 1 1 O
X GND 53 0 -2400 150 U 50 50 1 1 W
X D15 54 1000 -1700 300 L 50 50 1 1 B
X D14 55 1000 -1600 300 L 50 50 1 1 B
X D13 56 1000 -1500 300 L 50 50 1 1 B
X D12 57 1000 -1400 300 L 50 50 1 1 B
X D11 58 1000 -1300 300 L 50 50 1 1 B
X D10 59 1000 -1200 300 L 50 50 1 1 B
X AS 6 1000 -1900 300 L 50 50 1 1 O I
X D9 60 1000 -1100 300 L 50 50 1 1 B
X D8 61 1000 -1000 300 L 50 50 1 1 B
X D7 62 1000 -900 300 L 50 50 1 1 B
X D6 63 1000 -800 300 L 50 50 1 1 B
X D5 64 1000 -700 300 L 50 50 1 1 B
X UDS 7 1000 -2000 300 L 50 50 1 1 O I
X LDS 8 1000 -2100 300 L 50 50 1 1 O I
X R/W 9 1000 -2200 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# CPU_NXP_68000_68000D
#
DEF CPU_NXP_68000_68000D U 0 30 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "CPU_NXP_68000_68000D" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 68010D
DRAW
S -700 2250 700 -2250 0 1 10 f
X D4 1 1000 -600 300 L 50 50 1 1 B
X DTACK 10 -1000 -800 300 R 50 50 1 1 I I
X BG 11 -1000 1400 300 R 50 50 1 1 O I
X BGACK 12 -1000 1500 300 R 50 50 1 1 I I
X BR 13 -1000 1300 300 R 50 50 1 1 I I
X VCC 14 0 2400 150 D 50 50 1 1 W
X CLK 15 -1000 2200 300 R 50 50 1 1 I C
X GND 16 100 -2400 150 U 50 50 1 1 W
X HALT 17 -1000 -1200 300 R 50 50 1 1 B I
X RESET 18 -1000 -1300 300 R 50 50 1 1 B I
X VMA 19 -1000 500 300 R 50 50 1 1 O I
X D3 2 1000 -500 300 L 50 50 1 1 B
X E 20 -1000 400 300 R 50 50 1 1 O
X VPA 21 -1000 300 300 R 50 50 1 1 I I
X BERR 22 -1000 -600 300 R 50 50 1 1 I I
X IPL2 23 -1000 1700 300 R 50 50 1 1 I I
X IPL1 24 -1000 1800 300 R 50 50 1 1 I I
X IPL0 25 -1000 1900 300 R 50 50 1 1 I I
X FC2 26 -1000 800 300 R 50 50 1 1 O
X FC1 27 -1000 900 300 R 50 50 1 1 O
X FC0 28 -1000 1000 300 R 50 50 1 1 O
X A1 29 1000 2200 300 L 50 50 1 1 O
X D2 3 1000 -400 300 L 50 50 1 1 B
X A2 30 1000 2100 300 L 50 50 1 1 O
X A3 31 1000 2000 300 L 50 50 1 1 O
X A4 32 1000 1900 300 L 50 50 1 1 O
X A5 33 1000 1800 300 L 50 50 1 1 O
X A6 34 1000 1700 300 L 50 50 1 1 O
X A7 35 1000 1600 300 L 50 50 1 1 O
X A8 36 1000 1500 300 L 50 50 1 1 O
X A9 37 1000 1400 300 L 50 50 1 1 O
X A10 38 1000 1300 300 L 50 50 1 1 O
X A11 39 1000 1200 300 L 50 50 1 1 O
X D1 4 1000 -300 300 L 50 50 1 1 B
X A12 40 1000 1100 300 L 50 50 1 1 O
X A13 41 1000 1000 300 L 50 50 1 1 O
X A14 42 1000 900 300 L 50 50 1 1 O
X A15 43 1000 800 300 L 50 50 1 1 O
X A16 44 1000 700 300 L 50 50 1 1 O
X A17 45 1000 600 300 L 50 50 1 1 O
X A18 46 1000 500 300 L 50 50 1 1 O
X A19 47 1000 400 300 L 50 50 1 1 O
X A20 48 1000 300 300 L 50 50 1 1 O
X VCC 49 100 2400 150 D 50 50 1 1 W
X D0 5 1000 -200 300 L 50 50 1 1 B
X A21 50 1000 200 300 L 50 50 1 1 O
X A22 51 1000 100 300 L 50 50 1 1 O
X A23 52 1000 0 300 L 50 50 1 1 O
X GND 53 0 -2400 150 U 50 50 1 1 W
X D15 54 1000 -1700 300 L 50 50 1 1 B
X D14 55 1000 -1600 300 L 50 50 1 1 B
X D13 56 1000 -1500 300 L 50 50 1 1 B
X D12 57 1000 -1400 300 L 50 50 1 1 B
X D11 58 1000 -1300 300 L 50 50 1 1 B
X D10 59 1000 -1200 300 L 50 50 1 1 B
X AS 6 1000 -1900 300 L 50 50 1 1 O I
X D9 60 1000 -1100 300 L 50 50 1 1 B
X D8 61 1000 -1000 300 L 50 50 1 1 B
X D7 62 1000 -900 300 L 50 50 1 1 B
X D6 63 1000 -800 300 L 50 50 1 1 B
X D5 64 1000 -700 300 L 50 50 1 1 B
X UDS 7 1000 -2000 300 L 50 50 1 1 O I
X LDS 8 1000 -2100 300 L 50 50 1 1 O I
X R/W 9 1000 -2200 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
#End Library

297
AmiTech-Maximem-CPU-Adapter/AmiTech-Maximem-CPU-Adapter-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 18v8_18v8
#
DEF 18v8_18v8 U 0 40 Y Y 1 F N
F0 "U" -100 650 50 H V C CNN
F1 "18v8_18v8" 0 750 50 H V C CNN
F2 "" -50 -500 50 H I C CNN
F3 "" -50 -500 50 H I C CNN
DRAW
S -300 550 300 -550 0 1 0 N
X I/CLK 1 -400 450 100 R 50 50 1 1 I
X GND 10 0 -650 100 U 50 50 1 1 I
X I 11 -400 -450 100 R 50 50 1 1 I
X I/O 12 400 -350 100 L 50 50 1 1 B
X I/O 13 400 -250 100 L 50 50 1 1 B
X I/O 14 400 -150 100 L 50 50 1 1 B
X I/O 15 400 -50 100 L 50 50 1 1 B
X I/O 16 400 50 100 L 50 50 1 1 B
X I/O 17 400 150 100 L 50 50 1 1 B
X I/O 18 400 250 100 L 50 50 1 1 B
X I/O 19 400 350 100 L 50 50 1 1 B
X I 2 -400 350 100 R 50 50 1 1 I
X VCC 20 0 650 100 D 50 50 1 1 W
X I 3 -400 250 100 R 50 50 1 1 I
X I 4 -400 150 100 R 50 50 1 1 I
X I 5 -400 50 100 R 50 50 1 1 I
X I 6 -400 -50 100 R 50 50 1 1 I
X I 7 -400 -150 100 R 50 50 1 1 I
X I 8 -400 -250 100 R 50 50 1 1 I
X I 9 -400 -350 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# 18v8_64Pin_Socket
#
DEF 18v8_64Pin_Socket U 0 30 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "18v8_64Pin_Socket" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 68010D_copy
DRAW
S -700 2250 700 -2250 0 1 10 f
X D4 1 1000 -600 300 L 50 50 1 1 B
X DTACK 10 -1000 -800 300 R 50 50 1 1 I I
X BG 11 -1000 1400 300 R 50 50 1 1 O I
X BGACK 12 -1000 1500 300 R 50 50 1 1 I I
X BR 13 -1000 1300 300 R 50 50 1 1 I I
X VCC 14 0 2400 150 D 50 50 1 1 W
X CLK 15 -1000 2200 300 R 50 50 1 1 I C
X GND 16 100 -2400 150 U 50 50 1 1 W
X HALT 17 -1000 -1200 300 R 50 50 1 1 B I
X RESET 18 -1000 -1300 300 R 50 50 1 1 B I
X VMA 19 -1000 500 300 R 50 50 1 1 O I
X D3 2 1000 -500 300 L 50 50 1 1 B
X E 20 -1000 400 300 R 50 50 1 1 O
X VPA 21 -1000 300 300 R 50 50 1 1 I I
X BERR 22 -1000 -600 300 R 50 50 1 1 I I
X IPL2 23 -1000 1700 300 R 50 50 1 1 I I
X IPL1 24 -1000 1800 300 R 50 50 1 1 I I
X IPL0 25 -1000 1900 300 R 50 50 1 1 I I
X FC2 26 -1000 800 300 R 50 50 1 1 O
X FC1 27 -1000 900 300 R 50 50 1 1 O
X FC0 28 -1000 1000 300 R 50 50 1 1 O
X A1 29 1000 2200 300 L 50 50 1 1 O
X D2 3 1000 -400 300 L 50 50 1 1 B
X A2 30 1000 2100 300 L 50 50 1 1 O
X A3 31 1000 2000 300 L 50 50 1 1 O
X A4 32 1000 1900 300 L 50 50 1 1 O
X A5 33 1000 1800 300 L 50 50 1 1 O
X A6 34 1000 1700 300 L 50 50 1 1 O
X A7 35 1000 1600 300 L 50 50 1 1 O
X A8 36 1000 1500 300 L 50 50 1 1 O
X A9 37 1000 1400 300 L 50 50 1 1 O
X A10 38 1000 1300 300 L 50 50 1 1 O
X A11 39 1000 1200 300 L 50 50 1 1 O
X D1 4 1000 -300 300 L 50 50 1 1 B
X A12 40 1000 1100 300 L 50 50 1 1 O
X A13 41 1000 1000 300 L 50 50 1 1 O
X A14 42 1000 900 300 L 50 50 1 1 O
X A15 43 1000 800 300 L 50 50 1 1 O
X A16 44 1000 700 300 L 50 50 1 1 O
X A17 45 1000 600 300 L 50 50 1 1 O
X A18 46 1000 500 300 L 50 50 1 1 O
X A19 47 1000 400 300 L 50 50 1 1 O
X A20 48 1000 300 300 L 50 50 1 1 O
X VCC 49 100 2400 150 D 50 50 1 1 W
X D0 5 1000 -200 300 L 50 50 1 1 B
X A21 50 1000 200 300 L 50 50 1 1 O
X A22 51 1000 100 300 L 50 50 1 1 O
X A23 52 1000 0 300 L 50 50 1 1 O
X GND 53 0 -2400 150 U 50 50 1 1 W
X D15 54 1000 -1700 300 L 50 50 1 1 B
X D14 55 1000 -1600 300 L 50 50 1 1 B
X D13 56 1000 -1500 300 L 50 50 1 1 B
X D12 57 1000 -1400 300 L 50 50 1 1 B
X D11 58 1000 -1300 300 L 50 50 1 1 B
X D10 59 1000 -1200 300 L 50 50 1 1 B
X AS 6 1000 -1900 300 L 50 50 1 1 O I
X D9 60 1000 -1100 300 L 50 50 1 1 B
X D8 61 1000 -1000 300 L 50 50 1 1 B
X D7 62 1000 -900 300 L 50 50 1 1 B
X D6 63 1000 -800 300 L 50 50 1 1 B
X D5 64 1000 -700 300 L 50 50 1 1 B
X UDS 7 1000 -2000 300 L 50 50 1 1 O I
X LDS 8 1000 -2100 300 L 50 50 1 1 O I
X R/W 9 1000 -2200 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# CPU_NXP_68000_68000D
#
DEF CPU_NXP_68000_68000D U 0 30 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "CPU_NXP_68000_68000D" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 68010D
DRAW
S -700 2250 700 -2250 0 1 10 f
X D4 1 1000 -600 300 L 50 50 1 1 B
X DTACK 10 -1000 -800 300 R 50 50 1 1 I I
X BG 11 -1000 1400 300 R 50 50 1 1 O I
X BGACK 12 -1000 1500 300 R 50 50 1 1 I I
X BR 13 -1000 1300 300 R 50 50 1 1 I I
X VCC 14 0 2400 150 D 50 50 1 1 W
X CLK 15 -1000 2200 300 R 50 50 1 1 I C
X GND 16 100 -2400 150 U 50 50 1 1 W
X HALT 17 -1000 -1200 300 R 50 50 1 1 B I
X RESET 18 -1000 -1300 300 R 50 50 1 1 B I
X VMA 19 -1000 500 300 R 50 50 1 1 O I
X D3 2 1000 -500 300 L 50 50 1 1 B
X E 20 -1000 400 300 R 50 50 1 1 O
X VPA 21 -1000 300 300 R 50 50 1 1 I I
X BERR 22 -1000 -600 300 R 50 50 1 1 I I
X IPL2 23 -1000 1700 300 R 50 50 1 1 I I
X IPL1 24 -1000 1800 300 R 50 50 1 1 I I
X IPL0 25 -1000 1900 300 R 50 50 1 1 I I
X FC2 26 -1000 800 300 R 50 50 1 1 O
X FC1 27 -1000 900 300 R 50 50 1 1 O
X FC0 28 -1000 1000 300 R 50 50 1 1 O
X A1 29 1000 2200 300 L 50 50 1 1 O
X D2 3 1000 -400 300 L 50 50 1 1 B
X A2 30 1000 2100 300 L 50 50 1 1 O
X A3 31 1000 2000 300 L 50 50 1 1 O
X A4 32 1000 1900 300 L 50 50 1 1 O
X A5 33 1000 1800 300 L 50 50 1 1 O
X A6 34 1000 1700 300 L 50 50 1 1 O
X A7 35 1000 1600 300 L 50 50 1 1 O
X A8 36 1000 1500 300 L 50 50 1 1 O
X A9 37 1000 1400 300 L 50 50 1 1 O
X A10 38 1000 1300 300 L 50 50 1 1 O
X A11 39 1000 1200 300 L 50 50 1 1 O
X D1 4 1000 -300 300 L 50 50 1 1 B
X A12 40 1000 1100 300 L 50 50 1 1 O
X A13 41 1000 1000 300 L 50 50 1 1 O
X A14 42 1000 900 300 L 50 50 1 1 O
X A15 43 1000 800 300 L 50 50 1 1 O
X A16 44 1000 700 300 L 50 50 1 1 O
X A17 45 1000 600 300 L 50 50 1 1 O
X A18 46 1000 500 300 L 50 50 1 1 O
X A19 47 1000 400 300 L 50 50 1 1 O
X A20 48 1000 300 300 L 50 50 1 1 O
X VCC 49 100 2400 150 D 50 50 1 1 W
X D0 5 1000 -200 300 L 50 50 1 1 B
X A21 50 1000 200 300 L 50 50 1 1 O
X A22 51 1000 100 300 L 50 50 1 1 O
X A23 52 1000 0 300 L 50 50 1 1 O
X GND 53 0 -2400 150 U 50 50 1 1 W
X D15 54 1000 -1700 300 L 50 50 1 1 B
X D14 55 1000 -1600 300 L 50 50 1 1 B
X D13 56 1000 -1500 300 L 50 50 1 1 B
X D12 57 1000 -1400 300 L 50 50 1 1 B
X D11 58 1000 -1300 300 L 50 50 1 1 B
X D10 59 1000 -1200 300 L 50 50 1 1 B
X AS 6 1000 -1900 300 L 50 50 1 1 O I
X D9 60 1000 -1100 300 L 50 50 1 1 B
X D8 61 1000 -1000 300 L 50 50 1 1 B
X D7 62 1000 -900 300 L 50 50 1 1 B
X D6 63 1000 -800 300 L 50 50 1 1 B
X D5 64 1000 -700 300 L 50 50 1 1 B
X UDS 7 1000 -2000 300 L 50 50 1 1 O I
X LDS 8 1000 -2100 300 L 50 50 1 1 O I
X R/W 9 1000 -2200 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x06
#
DEF Connector_Generic_Conn_01x06 J 0 40 Y N 1 F N
F0 "J" 0 300 50 H V C CNN
F1 "Connector_Generic_Conn_01x06" 0 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 50 -350 1 1 10 f
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
X Pin_6 6 -200 -300 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Switch_SW_SPST
#
DEF Switch_SW_SPST SW 0 0 Y N 1 F N
F0 "SW" 0 125 50 H V C CNN
F1 "Switch_SW_SPST" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C -80 0 20 0 0 0 N
C 80 0 20 0 0 0 N
P 2 0 0 0 -60 10 60 70 N
X A 1 -200 0 100 R 50 50 1 1 P
X B 2 200 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GNDD
#
DEF power_GNDD #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GNDD" 0 -125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -50 -60 50 -80 0 1 10 F
P 2 0 1 0 0 0 0 -60 N
X GNDD 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

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AmiTech-Maximem-CPU-Adapter/AmiTech-Maximem-CPU-Adapter.kicad_pcb Normal file
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

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AmiTech-Maximem-CPU-Adapter/AmiTech-Maximem-CPU-Adapter.sch Normal file
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AmiTech-Maximem-CPU-Adapter/AmiTech-Maximem-CPU-Adapter_back.jpg Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 18v8_18v8
#
DEF 18v8_18v8 U 0 40 Y Y 1 F N
F0 "U" -100 650 50 H V C CNN
F1 "18v8_18v8" 0 750 50 H V C CNN
F2 "" -50 -500 50 H I C CNN
F3 "" -50 -500 50 H I C CNN
DRAW
S -300 550 300 -550 0 1 0 N
X I/CLK 1 -400 450 100 R 50 50 1 1 I
X GND 10 0 -650 100 U 50 50 1 1 I
X I 11 -400 -450 100 R 50 50 1 1 I
X I/O 12 400 -350 100 L 50 50 1 1 B
X I/O 13 400 -250 100 L 50 50 1 1 B
X I/O 14 400 -150 100 L 50 50 1 1 B
X I/O 15 400 -50 100 L 50 50 1 1 B
X I/O 16 400 50 100 L 50 50 1 1 B
X I/O 17 400 150 100 L 50 50 1 1 B
X I/O 18 400 250 100 L 50 50 1 1 B
X I/O 19 400 350 100 L 50 50 1 1 B
X I 2 -400 350 100 R 50 50 1 1 I
X VCC 20 0 650 100 D 50 50 1 1 W
X I 3 -400 250 100 R 50 50 1 1 I
X I 4 -400 150 100 R 50 50 1 1 I
X I 5 -400 50 100 R 50 50 1 1 I
X I 6 -400 -50 100 R 50 50 1 1 I
X I 7 -400 -150 100 R 50 50 1 1 I
X I 8 -400 -250 100 R 50 50 1 1 I
X I 9 -400 -350 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# 18v8_64Pin_Socket
#
DEF 18v8_64Pin_Socket U 0 30 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "18v8_64Pin_Socket" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 68010D_copy
DRAW
S -700 2250 700 -2250 0 1 10 f
X D4 1 1000 -600 300 L 50 50 1 1 B
X DTACK 10 -1000 -800 300 R 50 50 1 1 I I
X BG 11 -1000 1400 300 R 50 50 1 1 O I
X BGACK 12 -1000 1500 300 R 50 50 1 1 I I
X BR 13 -1000 1300 300 R 50 50 1 1 I I
X VCC 14 0 2400 150 D 50 50 1 1 W
X CLK 15 -1000 2200 300 R 50 50 1 1 I C
X GND 16 100 -2400 150 U 50 50 1 1 W
X HALT 17 -1000 -1200 300 R 50 50 1 1 B I
X RESET 18 -1000 -1300 300 R 50 50 1 1 B I
X VMA 19 -1000 500 300 R 50 50 1 1 O I
X D3 2 1000 -500 300 L 50 50 1 1 B
X E 20 -1000 400 300 R 50 50 1 1 O
X VPA 21 -1000 300 300 R 50 50 1 1 I I
X BERR 22 -1000 -600 300 R 50 50 1 1 I I
X IPL2 23 -1000 1700 300 R 50 50 1 1 I I
X IPL1 24 -1000 1800 300 R 50 50 1 1 I I
X IPL0 25 -1000 1900 300 R 50 50 1 1 I I
X FC2 26 -1000 800 300 R 50 50 1 1 O
X FC1 27 -1000 900 300 R 50 50 1 1 O
X FC0 28 -1000 1000 300 R 50 50 1 1 O
X A1 29 1000 2200 300 L 50 50 1 1 O
X D2 3 1000 -400 300 L 50 50 1 1 B
X A2 30 1000 2100 300 L 50 50 1 1 O
X A3 31 1000 2000 300 L 50 50 1 1 O
X A4 32 1000 1900 300 L 50 50 1 1 O
X A5 33 1000 1800 300 L 50 50 1 1 O
X A6 34 1000 1700 300 L 50 50 1 1 O
X A7 35 1000 1600 300 L 50 50 1 1 O
X A8 36 1000 1500 300 L 50 50 1 1 O
X A9 37 1000 1400 300 L 50 50 1 1 O
X A10 38 1000 1300 300 L 50 50 1 1 O
X A11 39 1000 1200 300 L 50 50 1 1 O
X D1 4 1000 -300 300 L 50 50 1 1 B
X A12 40 1000 1100 300 L 50 50 1 1 O
X A13 41 1000 1000 300 L 50 50 1 1 O
X A14 42 1000 900 300 L 50 50 1 1 O
X A15 43 1000 800 300 L 50 50 1 1 O
X A16 44 1000 700 300 L 50 50 1 1 O
X A17 45 1000 600 300 L 50 50 1 1 O
X A18 46 1000 500 300 L 50 50 1 1 O
X A19 47 1000 400 300 L 50 50 1 1 O
X A20 48 1000 300 300 L 50 50 1 1 O
X VCC 49 100 2400 150 D 50 50 1 1 W
X D0 5 1000 -200 300 L 50 50 1 1 B
X A21 50 1000 200 300 L 50 50 1 1 O
X A22 51 1000 100 300 L 50 50 1 1 O
X A23 52 1000 0 300 L 50 50 1 1 O
X GND 53 0 -2400 150 U 50 50 1 1 W
X D15 54 1000 -1700 300 L 50 50 1 1 B
X D14 55 1000 -1600 300 L 50 50 1 1 B
X D13 56 1000 -1500 300 L 50 50 1 1 B
X D12 57 1000 -1400 300 L 50 50 1 1 B
X D11 58 1000 -1300 300 L 50 50 1 1 B
X D10 59 1000 -1200 300 L 50 50 1 1 B
X AS 6 1000 -1900 300 L 50 50 1 1 O I
X D9 60 1000 -1100 300 L 50 50 1 1 B
X D8 61 1000 -1000 300 L 50 50 1 1 B
X D7 62 1000 -900 300 L 50 50 1 1 B
X D6 63 1000 -800 300 L 50 50 1 1 B
X D5 64 1000 -700 300 L 50 50 1 1 B
X UDS 7 1000 -2000 300 L 50 50 1 1 O I
X LDS 8 1000 -2100 300 L 50 50 1 1 O I
X R/W 9 1000 -2200 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# CPU_NXP_68000_68000D
#
DEF CPU_NXP_68000_68000D U 0 30 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "CPU_NXP_68000_68000D" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 68010D
DRAW
S -700 2250 700 -2250 0 1 10 f
X D4 1 1000 -600 300 L 50 50 1 1 B
X DTACK 10 -1000 -800 300 R 50 50 1 1 I I
X BG 11 -1000 1400 300 R 50 50 1 1 O I
X BGACK 12 -1000 1500 300 R 50 50 1 1 I I
X BR 13 -1000 1300 300 R 50 50 1 1 I I
X VCC 14 0 2400 150 D 50 50 1 1 W
X CLK 15 -1000 2200 300 R 50 50 1 1 I C
X GND 16 100 -2400 150 U 50 50 1 1 W
X HALT 17 -1000 -1200 300 R 50 50 1 1 B I
X RESET 18 -1000 -1300 300 R 50 50 1 1 B I
X VMA 19 -1000 500 300 R 50 50 1 1 O I
X D3 2 1000 -500 300 L 50 50 1 1 B
X E 20 -1000 400 300 R 50 50 1 1 O
X VPA 21 -1000 300 300 R 50 50 1 1 I I
X BERR 22 -1000 -600 300 R 50 50 1 1 I I
X IPL2 23 -1000 1700 300 R 50 50 1 1 I I
X IPL1 24 -1000 1800 300 R 50 50 1 1 I I
X IPL0 25 -1000 1900 300 R 50 50 1 1 I I
X FC2 26 -1000 800 300 R 50 50 1 1 O
X FC1 27 -1000 900 300 R 50 50 1 1 O
X FC0 28 -1000 1000 300 R 50 50 1 1 O
X A1 29 1000 2200 300 L 50 50 1 1 O
X D2 3 1000 -400 300 L 50 50 1 1 B
X A2 30 1000 2100 300 L 50 50 1 1 O
X A3 31 1000 2000 300 L 50 50 1 1 O
X A4 32 1000 1900 300 L 50 50 1 1 O
X A5 33 1000 1800 300 L 50 50 1 1 O
X A6 34 1000 1700 300 L 50 50 1 1 O
X A7 35 1000 1600 300 L 50 50 1 1 O
X A8 36 1000 1500 300 L 50 50 1 1 O
X A9 37 1000 1400 300 L 50 50 1 1 O
X A10 38 1000 1300 300 L 50 50 1 1 O
X A11 39 1000 1200 300 L 50 50 1 1 O
X D1 4 1000 -300 300 L 50 50 1 1 B
X A12 40 1000 1100 300 L 50 50 1 1 O
X A13 41 1000 1000 300 L 50 50 1 1 O
X A14 42 1000 900 300 L 50 50 1 1 O
X A15 43 1000 800 300 L 50 50 1 1 O
X A16 44 1000 700 300 L 50 50 1 1 O
X A17 45 1000 600 300 L 50 50 1 1 O
X A18 46 1000 500 300 L 50 50 1 1 O
X A19 47 1000 400 300 L 50 50 1 1 O
X A20 48 1000 300 300 L 50 50 1 1 O
X VCC 49 100 2400 150 D 50 50 1 1 W
X D0 5 1000 -200 300 L 50 50 1 1 B
X A21 50 1000 200 300 L 50 50 1 1 O
X A22 51 1000 100 300 L 50 50 1 1 O
X A23 52 1000 0 300 L 50 50 1 1 O
X GND 53 0 -2400 150 U 50 50 1 1 W
X D15 54 1000 -1700 300 L 50 50 1 1 B
X D14 55 1000 -1600 300 L 50 50 1 1 B
X D13 56 1000 -1500 300 L 50 50 1 1 B
X D12 57 1000 -1400 300 L 50 50 1 1 B
X D11 58 1000 -1300 300 L 50 50 1 1 B
X D10 59 1000 -1200 300 L 50 50 1 1 B
X AS 6 1000 -1900 300 L 50 50 1 1 O I
X D9 60 1000 -1100 300 L 50 50 1 1 B
X D8 61 1000 -1000 300 L 50 50 1 1 B
X D7 62 1000 -900 300 L 50 50 1 1 B
X D6 63 1000 -800 300 L 50 50 1 1 B
X D5 64 1000 -700 300 L 50 50 1 1 B
X UDS 7 1000 -2000 300 L 50 50 1 1 O I
X LDS 8 1000 -2100 300 L 50 50 1 1 O I
X R/W 9 1000 -2200 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x06
#
DEF Connector_Generic_Conn_01x06 J 0 40 Y N 1 F N
F0 "J" 0 300 50 H V C CNN
F1 "Connector_Generic_Conn_01x06" 0 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 50 -350 1 1 10 f
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
X Pin_6 6 -200 -300 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Switch_SW_SPST
#
DEF Switch_SW_SPST SW 0 0 Y N 1 F N
F0 "SW" 0 125 50 H V C CNN
F1 "Switch_SW_SPST" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C -80 0 20 0 0 0 N
C 80 0 20 0 0 0 N
P 2 0 0 0 -60 10 60 70 N
X A 1 -200 0 100 R 50 50 1 1 P
X B 2 200 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GNDD
#
DEF power_GNDD #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GNDD" 0 -125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -50 -60 50 -80 0 1 10 F
P 2 0 1 0 0 0 0 -60 N
X GNDD 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

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(export (version D)
(design
(source D:\CloudDrives\NextCloud\tomses-projects\AmiTech-Maximem\AmiTech-Maximem.sch)
(date "01/12/20 20:10:56")
(tool "Eeschema (5.1.5)-3")
(sheet (number 1) (name /) (tstamps /)
(title_block
(title "AmiTech MaxiMem CPU Adapter")
(company)
(rev 1.0)
(date)
(source AmiTech-Maximem.sch)
(comment (number 1) (value ""))
(comment (number 2) (value ""))
(comment (number 3) (value http://retro-commodore.eu))
(comment (number 4) (value "Author: Tomse / Carsten Jensen")))))
(components
(comp (ref U1)
(value 68000D)
(footprint Package_DIP:DIP-64_W25.4mm_Socket_LongPads)
(datasheet https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf)
(libsource (lib CPU_NXP_68000) (part 68000D) (description "16/32-bit Microprocessor"))
(sheetpath (names /) (tstamps /))
(tstamp 5E1A4529))
(comp (ref SW1)
(value SW_SPST)
(footprint Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical)
(datasheet ~)
(libsource (lib Switch) (part SW_SPST) (description "Single Pole Single Throw (SPST) switch"))
(sheetpath (names /) (tstamps /))
(tstamp 5E1A7FB0))
(comp (ref U3)
(value 18v8)
(footprint Package_DIP:DIP-20_W7.62mm_Socket)
(libsource (lib 18v8) (part 18v8) (description ""))
(sheetpath (names /) (tstamps /))
(tstamp 5E1B7C58))
(comp (ref R1)
(value 10K)
(footprint Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal)
(datasheet ~)
(libsource (lib Device) (part R) (description Resistor))
(sheetpath (names /) (tstamps /))
(tstamp 5E1B971D))
(comp (ref C1)
(value 100nF)
(footprint Capacitor_THT:C_Axial_L5.1mm_D3.1mm_P7.50mm_Horizontal)
(datasheet ~)
(libsource (lib Device) (part C) (description "Unpolarized capacitor"))
(sheetpath (names /) (tstamps /))
(tstamp 5E1BA1F0))
(comp (ref U2)
(value 64Pin_Socket)
(footprint AmiTech-Maximem:DIP-64_W25.4mm_Socket_LongPads_noSilk)
(datasheet https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf)
(libsource (lib 18v8) (part 64Pin_Socket) (description "16/32-bit Microprocessor"))
(sheetpath (names /) (tstamps /))
(tstamp 5E1BD759))
(comp (ref J1)
(value Conn_01x06)
(footprint Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical)
(datasheet ~)
(libsource (lib Connector_Generic) (part Conn_01x06) (description "Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)"))
(sheetpath (names /) (tstamps /))
(tstamp 5ECF33B6)))
(libparts
(libpart (lib 18v8) (part 18v8)
(fields
(field (name Reference) U)
(field (name Value) 18v8))
(pins
(pin (num 1) (name I/CLK) (type input))
(pin (num 2) (name I) (type input))
(pin (num 3) (name I) (type input))
(pin (num 4) (name I) (type input))
(pin (num 5) (name I) (type input))
(pin (num 6) (name I) (type input))
(pin (num 7) (name I) (type input))
(pin (num 8) (name I) (type input))
(pin (num 9) (name I) (type input))
(pin (num 10) (name GND) (type input))
(pin (num 11) (name I) (type input))
(pin (num 12) (name I/O) (type BiDi))
(pin (num 13) (name I/O) (type BiDi))
(pin (num 14) (name I/O) (type BiDi))
(pin (num 15) (name I/O) (type BiDi))
(pin (num 16) (name I/O) (type BiDi))
(pin (num 17) (name I/O) (type BiDi))
(pin (num 18) (name I/O) (type BiDi))
(pin (num 19) (name I/O) (type BiDi))
(pin (num 20) (name VCC) (type power_in))))
(libpart (lib 18v8) (part 64Pin_Socket)
(aliases
(alias 68010D_copy))
(description "16/32-bit Microprocessor")
(docs https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf)
(fields
(field (name Reference) U)
(field (name Value) 64Pin_Socket))
(pins
(pin (num 1) (name D4) (type BiDi))
(pin (num 2) (name D3) (type BiDi))
(pin (num 3) (name D2) (type BiDi))
(pin (num 4) (name D1) (type BiDi))
(pin (num 5) (name D0) (type BiDi))
(pin (num 6) (name AS) (type output))
(pin (num 7) (name UDS) (type output))
(pin (num 8) (name LDS) (type output))
(pin (num 9) (name R/W) (type output))
(pin (num 10) (name DTACK) (type input))
(pin (num 11) (name BG) (type output))
(pin (num 12) (name BGACK) (type input))
(pin (num 13) (name BR) (type input))
(pin (num 14) (name VCC) (type power_in))
(pin (num 15) (name CLK) (type input))
(pin (num 16) (name GND) (type power_in))
(pin (num 17) (name HALT) (type BiDi))
(pin (num 18) (name RESET) (type BiDi))
(pin (num 19) (name VMA) (type output))
(pin (num 20) (name E) (type output))
(pin (num 21) (name VPA) (type input))
(pin (num 22) (name BERR) (type input))
(pin (num 23) (name IPL2) (type input))
(pin (num 24) (name IPL1) (type input))
(pin (num 25) (name IPL0) (type input))
(pin (num 26) (name FC2) (type output))
(pin (num 27) (name FC1) (type output))
(pin (num 28) (name FC0) (type output))
(pin (num 29) (name A1) (type output))
(pin (num 30) (name A2) (type output))
(pin (num 31) (name A3) (type output))
(pin (num 32) (name A4) (type output))
(pin (num 33) (name A5) (type output))
(pin (num 34) (name A6) (type output))
(pin (num 35) (name A7) (type output))
(pin (num 36) (name A8) (type output))
(pin (num 37) (name A9) (type output))
(pin (num 38) (name A10) (type output))
(pin (num 39) (name A11) (type output))
(pin (num 40) (name A12) (type output))
(pin (num 41) (name A13) (type output))
(pin (num 42) (name A14) (type output))
(pin (num 43) (name A15) (type output))
(pin (num 44) (name A16) (type output))
(pin (num 45) (name A17) (type output))
(pin (num 46) (name A18) (type output))
(pin (num 47) (name A19) (type output))
(pin (num 48) (name A20) (type output))
(pin (num 49) (name VCC) (type power_in))
(pin (num 50) (name A21) (type output))
(pin (num 51) (name A22) (type output))
(pin (num 52) (name A23) (type output))
(pin (num 53) (name GND) (type power_in))
(pin (num 54) (name D15) (type BiDi))
(pin (num 55) (name D14) (type BiDi))
(pin (num 56) (name D13) (type BiDi))
(pin (num 57) (name D12) (type BiDi))
(pin (num 58) (name D11) (type BiDi))
(pin (num 59) (name D10) (type BiDi))
(pin (num 60) (name D9) (type BiDi))
(pin (num 61) (name D8) (type BiDi))
(pin (num 62) (name D7) (type BiDi))
(pin (num 63) (name D6) (type BiDi))
(pin (num 64) (name D5) (type BiDi))))
(libpart (lib CPU_NXP_68000) (part 68000D)
(aliases
(alias 68010D))
(description "16/32-bit Microprocessor")
(docs https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf)
(fields
(field (name Reference) U)
(field (name Value) 68000D))
(pins
(pin (num 1) (name D4) (type BiDi))
(pin (num 2) (name D3) (type BiDi))
(pin (num 3) (name D2) (type BiDi))
(pin (num 4) (name D1) (type BiDi))
(pin (num 5) (name D0) (type BiDi))
(pin (num 6) (name AS) (type output))
(pin (num 7) (name UDS) (type output))
(pin (num 8) (name LDS) (type output))
(pin (num 9) (name R/W) (type output))
(pin (num 10) (name DTACK) (type input))
(pin (num 11) (name BG) (type output))
(pin (num 12) (name BGACK) (type input))
(pin (num 13) (name BR) (type input))
(pin (num 14) (name VCC) (type power_in))
(pin (num 15) (name CLK) (type input))
(pin (num 16) (name GND) (type power_in))
(pin (num 17) (name HALT) (type BiDi))
(pin (num 18) (name RESET) (type BiDi))
(pin (num 19) (name VMA) (type output))
(pin (num 20) (name E) (type output))
(pin (num 21) (name VPA) (type input))
(pin (num 22) (name BERR) (type input))
(pin (num 23) (name IPL2) (type input))
(pin (num 24) (name IPL1) (type input))
(pin (num 25) (name IPL0) (type input))
(pin (num 26) (name FC2) (type output))
(pin (num 27) (name FC1) (type output))
(pin (num 28) (name FC0) (type output))
(pin (num 29) (name A1) (type output))
(pin (num 30) (name A2) (type output))
(pin (num 31) (name A3) (type output))
(pin (num 32) (name A4) (type output))
(pin (num 33) (name A5) (type output))
(pin (num 34) (name A6) (type output))
(pin (num 35) (name A7) (type output))
(pin (num 36) (name A8) (type output))
(pin (num 37) (name A9) (type output))
(pin (num 38) (name A10) (type output))
(pin (num 39) (name A11) (type output))
(pin (num 40) (name A12) (type output))
(pin (num 41) (name A13) (type output))
(pin (num 42) (name A14) (type output))
(pin (num 43) (name A15) (type output))
(pin (num 44) (name A16) (type output))
(pin (num 45) (name A17) (type output))
(pin (num 46) (name A18) (type output))
(pin (num 47) (name A19) (type output))
(pin (num 48) (name A20) (type output))
(pin (num 49) (name VCC) (type power_in))
(pin (num 50) (name A21) (type output))
(pin (num 51) (name A22) (type output))
(pin (num 52) (name A23) (type output))
(pin (num 53) (name GND) (type power_in))
(pin (num 54) (name D15) (type BiDi))
(pin (num 55) (name D14) (type BiDi))
(pin (num 56) (name D13) (type BiDi))
(pin (num 57) (name D12) (type BiDi))
(pin (num 58) (name D11) (type BiDi))
(pin (num 59) (name D10) (type BiDi))
(pin (num 60) (name D9) (type BiDi))
(pin (num 61) (name D8) (type BiDi))
(pin (num 62) (name D7) (type BiDi))
(pin (num 63) (name D6) (type BiDi))
(pin (num 64) (name D5) (type BiDi))))
(libpart (lib Connector_Generic) (part Conn_01x06)
(description "Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)")
(docs ~)
(footprints
(fp Connector*:*_1x??_*))
(fields
(field (name Reference) J)
(field (name Value) Conn_01x06))
(pins
(pin (num 1) (name Pin_1) (type passive))
(pin (num 2) (name Pin_2) (type passive))
(pin (num 3) (name Pin_3) (type passive))
(pin (num 4) (name Pin_4) (type passive))
(pin (num 5) (name Pin_5) (type passive))
(pin (num 6) (name Pin_6) (type passive))))
(libpart (lib Device) (part C)
(description "Unpolarized capacitor")
(docs ~)
(footprints
(fp C_*))
(fields
(field (name Reference) C)
(field (name Value) C))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib Device) (part R)
(description Resistor)
(docs ~)
(footprints
(fp R_*))
(fields
(field (name Reference) R)
(field (name Value) R))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib Switch) (part SW_SPST)
(description "Single Pole Single Throw (SPST) switch")
(docs ~)
(fields
(field (name Reference) SW)
(field (name Value) SW_SPST))
(pins
(pin (num 1) (name A) (type passive))
(pin (num 2) (name B) (type passive)))))
(libraries
(library (logical 18v8)
(uri D:\CloudDrives\NextCloud\tomses-projects\AmiTech-Maximem/18v8.lib))
(library (logical CPU_NXP_68000)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library/CPU_NXP_68000.lib"))
(library (logical Connector_Generic)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library/Connector_Generic.lib"))
(library (logical Device)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library/Device.lib"))
(library (logical Switch)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library/Switch.lib")))
(nets
(net (code 1) (name GNDD)
(node (ref C1) (pin 1))
(node (ref SW1) (pin 2))
(node (ref U3) (pin 10))
(node (ref U2) (pin 53))
(node (ref U1) (pin 53))
(node (ref U1) (pin 16))
(node (ref U2) (pin 16)))
(net (code 2) (name /A22)
(node (ref U3) (pin 7))
(node (ref U2) (pin 51)))
(net (code 3) (name /A14)
(node (ref U2) (pin 42))
(node (ref U1) (pin 42)))
(net (code 4) (name /A15)
(node (ref U2) (pin 43))
(node (ref U1) (pin 43)))
(net (code 5) (name /A16)
(node (ref U2) (pin 44))
(node (ref U1) (pin 44)))
(net (code 6) (name /A17)
(node (ref U2) (pin 45))
(node (ref U1) (pin 45)))
(net (code 7) (name /A18)
(node (ref U1) (pin 46))
(node (ref U2) (pin 46)))
(net (code 8) (name /A19)
(node (ref U2) (pin 47))
(node (ref U3) (pin 11)))
(net (code 9) (name /A20)
(node (ref U2) (pin 48))
(node (ref U1) (pin 48))
(node (ref U3) (pin 9)))
(net (code 10) (name /A21)
(node (ref U2) (pin 50))
(node (ref U1) (pin 50))
(node (ref U3) (pin 8)))
(net (code 11) (name /A13)
(node (ref U2) (pin 41))
(node (ref U1) (pin 41)))
(net (code 12) (name /A23)
(node (ref U3) (pin 6))
(node (ref U2) (pin 52)))
(net (code 13) (name /D0)
(node (ref U1) (pin 5))
(node (ref U2) (pin 5)))
(net (code 14) (name /D1)
(node (ref U1) (pin 4))
(node (ref U2) (pin 4)))
(net (code 15) (name /D2)
(node (ref U1) (pin 3))
(node (ref U2) (pin 3)))
(net (code 16) (name /D3)
(node (ref U1) (pin 2))
(node (ref U2) (pin 2)))
(net (code 17) (name /D4)
(node (ref U2) (pin 1))
(node (ref U1) (pin 1)))
(net (code 18) (name /A12)
(node (ref U2) (pin 40))
(node (ref U1) (pin 40)))
(net (code 19) (name /A11)
(node (ref U2) (pin 39))
(node (ref U1) (pin 39)))
(net (code 20) (name /A10)
(node (ref U2) (pin 38))
(node (ref U1) (pin 38)))
(net (code 21) (name /A9)
(node (ref U2) (pin 37))
(node (ref U1) (pin 37)))
(net (code 22) (name /A8)
(node (ref U1) (pin 36))
(node (ref U2) (pin 36)))
(net (code 23) (name /A7)
(node (ref U1) (pin 35))
(node (ref U2) (pin 35)))
(net (code 24) (name /A6)
(node (ref U1) (pin 34))
(node (ref U2) (pin 34)))
(net (code 25) (name /A5)
(node (ref U2) (pin 33))
(node (ref U1) (pin 33)))
(net (code 26) (name /A4)
(node (ref U2) (pin 32))
(node (ref U1) (pin 32)))
(net (code 27) (name /A3)
(node (ref U1) (pin 31))
(node (ref U2) (pin 31)))
(net (code 28) (name /A2)
(node (ref U1) (pin 30))
(node (ref U2) (pin 30)))
(net (code 29) (name /A1)
(node (ref U1) (pin 29))
(node (ref U2) (pin 29)))
(net (code 30) (name /BERR)
(node (ref U1) (pin 22))
(node (ref U2) (pin 22)))
(net (code 32) (name /AS)
(node (ref U1) (pin 6))
(node (ref U2) (pin 6))
(node (ref U3) (pin 5)))
(net (code 33) (name /D15)
(node (ref U2) (pin 54))
(node (ref U1) (pin 54)))
(net (code 34) (name /D14)
(node (ref U2) (pin 55))
(node (ref U1) (pin 55)))
(net (code 35) (name /D13)
(node (ref U2) (pin 56))
(node (ref U1) (pin 56)))
(net (code 36) (name /D12)
(node (ref U1) (pin 57))
(node (ref U2) (pin 57)))
(net (code 37) (name /D11)
(node (ref U2) (pin 58))
(node (ref U1) (pin 58)))
(net (code 38) (name /D10)
(node (ref U2) (pin 59))
(node (ref U1) (pin 59)))
(net (code 39) (name /D9)
(node (ref U1) (pin 60))
(node (ref U2) (pin 60)))
(net (code 40) (name "Net-(J1-Pad5)")
(node (ref U3) (pin 3))
(node (ref J1) (pin 5)))
(net (code 41) (name "Net-(J1-Pad6)")
(node (ref U3) (pin 4))
(node (ref J1) (pin 6)))
(net (code 43) (name "Net-(J1-Pad3)")
(node (ref SW1) (pin 1))
(node (ref J1) (pin 3))
(node (ref R1) (pin 2))
(node (ref U3) (pin 2)))
(net (code 44) (name "Net-(J1-Pad4)")
(node (ref J1) (pin 4))
(node (ref U3) (pin 1)))
(net (code 45) (name "Net-(J1-Pad1)")
(node (ref U3) (pin 14))
(node (ref J1) (pin 1)))
(net (code 46) (name "Net-(J1-Pad2)")
(node (ref U3) (pin 13))
(node (ref J1) (pin 2)))
(net (code 47) (name +5V)
(node (ref U1) (pin 14))
(node (ref U2) (pin 14))
(node (ref U2) (pin 49))
(node (ref U1) (pin 49))
(node (ref U3) (pin 20))
(node (ref R1) (pin 1))
(node (ref C1) (pin 2)))
(net (code 48) (name /RW)
(node (ref U2) (pin 9))
(node (ref U1) (pin 9)))
(net (code 49) (name /LDS)
(node (ref U2) (pin 8))
(node (ref U1) (pin 8)))
(net (code 50) (name /UDS)
(node (ref U2) (pin 7))
(node (ref U1) (pin 7)))
(net (code 51) (name /D5)
(node (ref U1) (pin 64))
(node (ref U2) (pin 64)))
(net (code 52) (name /D6)
(node (ref U1) (pin 63))
(node (ref U2) (pin 63)))
(net (code 53) (name /D7)
(node (ref U1) (pin 62))
(node (ref U2) (pin 62)))
(net (code 54) (name /D8)
(node (ref U1) (pin 61))
(node (ref U2) (pin 61)))
(net (code 55) (name /FC2)
(node (ref U1) (pin 26))
(node (ref U2) (pin 26)))
(net (code 56) (name /RESET)
(node (ref U2) (pin 18))
(node (ref U1) (pin 18)))
(net (code 57) (name /HALT)
(node (ref U2) (pin 17))
(node (ref U1) (pin 17)))
(net (code 58) (name /DTACK)
(node (ref U1) (pin 10))
(node (ref U2) (pin 10)))
(net (code 59) (name /VPA)
(node (ref U1) (pin 21))
(node (ref U2) (pin 21)))
(net (code 60) (name /E)
(node (ref U1) (pin 20))
(node (ref U2) (pin 20)))
(net (code 61) (name /VMA)
(node (ref U1) (pin 19))
(node (ref U2) (pin 19)))
(net (code 62) (name /FC1)
(node (ref U2) (pin 27))
(node (ref U1) (pin 27)))
(net (code 63) (name /FC0)
(node (ref U2) (pin 28))
(node (ref U1) (pin 28)))
(net (code 64) (name /BR)
(node (ref U1) (pin 13))
(node (ref U2) (pin 13)))
(net (code 65) (name /BG)
(node (ref U2) (pin 11))
(node (ref U1) (pin 11)))
(net (code 66) (name /IPL2)
(node (ref U1) (pin 23))
(node (ref U2) (pin 23)))
(net (code 67) (name /IPL1)
(node (ref U2) (pin 24))
(node (ref U1) (pin 24)))
(net (code 68) (name /IPL0)
(node (ref U2) (pin 25))
(node (ref U1) (pin 25)))
(net (code 69) (name /CLK)
(node (ref U1) (pin 15))
(node (ref U2) (pin 15)))
(net (code 70) (name /BGACK)
(node (ref U2) (pin 12))
(node (ref U1) (pin 12))
(node (ref U3) (pin 19)))
(net (code 71) (name "Net-(U3-Pad18)")
(node (ref U3) (pin 18)))
(net (code 72) (name /A23_M)
(node (ref U3) (pin 17))
(node (ref U1) (pin 52)))
(net (code 73) (name "Net-(U3-Pad16)")
(node (ref U3) (pin 16)))
(net (code 74) (name /A22_M)
(node (ref U1) (pin 51))
(node (ref U3) (pin 15)))
(net (code 75) (name /A19_M)
(node (ref U3) (pin 12))
(node (ref U1) (pin 47)))))

248
AmiTech-Maximem-CPU-Adapter/AmiTech-Maximem.pro Normal file
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@ -0,0 +1,248 @@
update=01/12/20 01:08:30
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=AmiTech-Maximem.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=1
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

1115
AmiTech-Maximem-CPU-Adapter/AmiTech-Maximem.sch-bak Normal file
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File diff suppressed because it is too large Load Diff

BIN
AmiTech-Maximem-CPU-Adapter/_autosave-AmiTech-Maximem-backups/_autosave-AmiTech-Maximem-2023-12-21_194859.zip Normal file
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295
AmiTech-Maximem-CPU-Adapter/_autosave-AmiTech-Maximem-cache.lib Normal file
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@ -0,0 +1,295 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 18v8_18v8
#
DEF 18v8_18v8 U 0 40 Y Y 1 F N
F0 "U" -100 650 50 H V C CNN
F1 "18v8_18v8" 0 750 50 H V C CNN
F2 "" -50 -500 50 H I C CNN
F3 "" -50 -500 50 H I C CNN
DRAW
S -300 550 300 -550 0 1 0 N
X I/CLK 1 -400 450 100 R 50 50 1 1 I
X GND 10 0 -650 100 U 50 50 1 1 I
X I 11 -400 -450 100 R 50 50 1 1 I
X I/O 12 400 -350 100 L 50 50 1 1 B
X I/O 13 400 -250 100 L 50 50 1 1 B
X I/O 14 400 -150 100 L 50 50 1 1 B
X I/O 15 400 -50 100 L 50 50 1 1 B
X I/O 16 400 50 100 L 50 50 1 1 B
X I/O 17 400 150 100 L 50 50 1 1 B
X I/O 18 400 250 100 L 50 50 1 1 B
X I/O 19 400 350 100 L 50 50 1 1 B
X I 2 -400 350 100 R 50 50 1 1 I
X VCC 20 0 650 100 D 50 50 1 1 W
X I 3 -400 250 100 R 50 50 1 1 I
X I 4 -400 150 100 R 50 50 1 1 I
X I 5 -400 50 100 R 50 50 1 1 I
X I 6 -400 -50 100 R 50 50 1 1 I
X I 7 -400 -150 100 R 50 50 1 1 I
X I 8 -400 -250 100 R 50 50 1 1 I
X I 9 -400 -350 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# 18v8_64Pin_Socket
#
DEF 18v8_64Pin_Socket U 0 30 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "18v8_64Pin_Socket" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 68010D_copy
DRAW
S -700 2250 700 -2250 0 1 10 f
X D4 1 1000 -600 300 L 50 50 1 1 B
X DTACK 10 -1000 -800 300 R 50 50 1 1 I I
X BG 11 -1000 1400 300 R 50 50 1 1 O I
X BGACK 12 -1000 1500 300 R 50 50 1 1 I I
X BR 13 -1000 1300 300 R 50 50 1 1 I I
X VCC 14 0 2400 150 D 50 50 1 1 W
X CLK 15 -1000 2200 300 R 50 50 1 1 I C
X GND 16 100 -2400 150 U 50 50 1 1 W
X HALT 17 -1000 -1200 300 R 50 50 1 1 B I
X RESET 18 -1000 -1300 300 R 50 50 1 1 B I
X VMA 19 -1000 500 300 R 50 50 1 1 O I
X D3 2 1000 -500 300 L 50 50 1 1 B
X E 20 -1000 400 300 R 50 50 1 1 O
X VPA 21 -1000 300 300 R 50 50 1 1 I I
X BERR 22 -1000 -600 300 R 50 50 1 1 I I
X IPL2 23 -1000 1700 300 R 50 50 1 1 I I
X IPL1 24 -1000 1800 300 R 50 50 1 1 I I
X IPL0 25 -1000 1900 300 R 50 50 1 1 I I
X FC2 26 -1000 800 300 R 50 50 1 1 O
X FC1 27 -1000 900 300 R 50 50 1 1 O
X FC0 28 -1000 1000 300 R 50 50 1 1 O
X A1 29 1000 2200 300 L 50 50 1 1 O
X D2 3 1000 -400 300 L 50 50 1 1 B
X A2 30 1000 2100 300 L 50 50 1 1 O
X A3 31 1000 2000 300 L 50 50 1 1 O
X A4 32 1000 1900 300 L 50 50 1 1 O
X A5 33 1000 1800 300 L 50 50 1 1 O
X A6 34 1000 1700 300 L 50 50 1 1 O
X A7 35 1000 1600 300 L 50 50 1 1 O
X A8 36 1000 1500 300 L 50 50 1 1 O
X A9 37 1000 1400 300 L 50 50 1 1 O
X A10 38 1000 1300 300 L 50 50 1 1 O
X A11 39 1000 1200 300 L 50 50 1 1 O
X D1 4 1000 -300 300 L 50 50 1 1 B
X A12 40 1000 1100 300 L 50 50 1 1 O
X A13 41 1000 1000 300 L 50 50 1 1 O
X A14 42 1000 900 300 L 50 50 1 1 O
X A15 43 1000 800 300 L 50 50 1 1 O
X A16 44 1000 700 300 L 50 50 1 1 O
X A17 45 1000 600 300 L 50 50 1 1 O
X A18 46 1000 500 300 L 50 50 1 1 O
X A19 47 1000 400 300 L 50 50 1 1 O
X A20 48 1000 300 300 L 50 50 1 1 O
X VCC 49 100 2400 150 D 50 50 1 1 W
X D0 5 1000 -200 300 L 50 50 1 1 B
X A21 50 1000 200 300 L 50 50 1 1 O
X A22 51 1000 100 300 L 50 50 1 1 O
X A23 52 1000 0 300 L 50 50 1 1 O
X GND 53 0 -2400 150 U 50 50 1 1 W
X D15 54 1000 -1700 300 L 50 50 1 1 B
X D14 55 1000 -1600 300 L 50 50 1 1 B
X D13 56 1000 -1500 300 L 50 50 1 1 B
X D12 57 1000 -1400 300 L 50 50 1 1 B
X D11 58 1000 -1300 300 L 50 50 1 1 B
X D10 59 1000 -1200 300 L 50 50 1 1 B
X AS 6 1000 -1900 300 L 50 50 1 1 O I
X D9 60 1000 -1100 300 L 50 50 1 1 B
X D8 61 1000 -1000 300 L 50 50 1 1 B
X D7 62 1000 -900 300 L 50 50 1 1 B
X D6 63 1000 -800 300 L 50 50 1 1 B
X D5 64 1000 -700 300 L 50 50 1 1 B
X UDS 7 1000 -2000 300 L 50 50 1 1 O I
X LDS 8 1000 -2100 300 L 50 50 1 1 O I
X R/W 9 1000 -2200 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# CPU_NXP_68000_68000D
#
DEF CPU_NXP_68000_68000D U 0 30 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "CPU_NXP_68000_68000D" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 68010D
DRAW
S -700 2250 700 -2250 0 1 10 f
X D4 1 1000 -600 300 L 50 50 1 1 B
X DTACK 10 -1000 -800 300 R 50 50 1 1 I I
X BG 11 -1000 1400 300 R 50 50 1 1 O I
X BGACK 12 -1000 1500 300 R 50 50 1 1 I I
X BR 13 -1000 1300 300 R 50 50 1 1 I I
X VCC 14 0 2400 150 D 50 50 1 1 W
X CLK 15 -1000 2200 300 R 50 50 1 1 I C
X GND 16 100 -2400 150 U 50 50 1 1 W
X HALT 17 -1000 -1200 300 R 50 50 1 1 B I
X RESET 18 -1000 -1300 300 R 50 50 1 1 B I
X VMA 19 -1000 500 300 R 50 50 1 1 O I
X D3 2 1000 -500 300 L 50 50 1 1 B
X E 20 -1000 400 300 R 50 50 1 1 O
X VPA 21 -1000 300 300 R 50 50 1 1 I I
X BERR 22 -1000 -600 300 R 50 50 1 1 I I
X IPL2 23 -1000 1700 300 R 50 50 1 1 I I
X IPL1 24 -1000 1800 300 R 50 50 1 1 I I
X IPL0 25 -1000 1900 300 R 50 50 1 1 I I
X FC2 26 -1000 800 300 R 50 50 1 1 O
X FC1 27 -1000 900 300 R 50 50 1 1 O
X FC0 28 -1000 1000 300 R 50 50 1 1 O
X A1 29 1000 2200 300 L 50 50 1 1 O
X D2 3 1000 -400 300 L 50 50 1 1 B
X A2 30 1000 2100 300 L 50 50 1 1 O
X A3 31 1000 2000 300 L 50 50 1 1 O
X A4 32 1000 1900 300 L 50 50 1 1 O
X A5 33 1000 1800 300 L 50 50 1 1 O
X A6 34 1000 1700 300 L 50 50 1 1 O
X A7 35 1000 1600 300 L 50 50 1 1 O
X A8 36 1000 1500 300 L 50 50 1 1 O
X A9 37 1000 1400 300 L 50 50 1 1 O
X A10 38 1000 1300 300 L 50 50 1 1 O
X A11 39 1000 1200 300 L 50 50 1 1 O
X D1 4 1000 -300 300 L 50 50 1 1 B
X A12 40 1000 1100 300 L 50 50 1 1 O
X A13 41 1000 1000 300 L 50 50 1 1 O
X A14 42 1000 900 300 L 50 50 1 1 O
X A15 43 1000 800 300 L 50 50 1 1 O
X A16 44 1000 700 300 L 50 50 1 1 O
X A17 45 1000 600 300 L 50 50 1 1 O
X A18 46 1000 500 300 L 50 50 1 1 O
X A19 47 1000 400 300 L 50 50 1 1 O
X A20 48 1000 300 300 L 50 50 1 1 O
X VCC 49 100 2400 150 D 50 50 1 1 W
X D0 5 1000 -200 300 L 50 50 1 1 B
X A21 50 1000 200 300 L 50 50 1 1 O
X A22 51 1000 100 300 L 50 50 1 1 O
X A23 52 1000 0 300 L 50 50 1 1 O
X GND 53 0 -2400 150 U 50 50 1 1 W
X D15 54 1000 -1700 300 L 50 50 1 1 B
X D14 55 1000 -1600 300 L 50 50 1 1 B
X D13 56 1000 -1500 300 L 50 50 1 1 B
X D12 57 1000 -1400 300 L 50 50 1 1 B
X D11 58 1000 -1300 300 L 50 50 1 1 B
X D10 59 1000 -1200 300 L 50 50 1 1 B
X AS 6 1000 -1900 300 L 50 50 1 1 O I
X D9 60 1000 -1100 300 L 50 50 1 1 B
X D8 61 1000 -1000 300 L 50 50 1 1 B
X D7 62 1000 -900 300 L 50 50 1 1 B
X D6 63 1000 -800 300 L 50 50 1 1 B
X D5 64 1000 -700 300 L 50 50 1 1 B
X UDS 7 1000 -2000 300 L 50 50 1 1 O I
X LDS 8 1000 -2100 300 L 50 50 1 1 O I
X R/W 9 1000 -2200 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x05
#
DEF Connector_Generic_Conn_01x05 J 0 40 Y N 1 F N
F0 "J" 0 300 50 H V C CNN
F1 "Connector_Generic_Conn_01x05" 0 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 50 -250 1 1 10 f
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Switch_SW_SPST
#
DEF Switch_SW_SPST SW 0 0 Y N 1 F N
F0 "SW" 0 125 50 H V C CNN
F1 "Switch_SW_SPST" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C -80 0 20 0 0 0 N
C 80 0 20 0 0 0 N
P 2 0 0 0 -60 10 60 70 N
X A 1 -200 0 100 R 50 50 1 1 P
X B 2 200 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GNDD
#
DEF power_GNDD #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GNDD" 0 -125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -50 -60 50 -80 0 1 10 F
P 2 0 1 0 0 0 0 -60 N
X GNDD 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

77
AmiTech-Maximem-CPU-Adapter/_autosave-AmiTech-Maximem.kicad_prl Normal file
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@ -0,0 +1,77 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
15,
16,
17,
18,
19,
20,
21,
22,
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AmiTech-Maximem-CPU-Adapter/_autosave-AmiTech-Maximem.kicad_pro Normal file
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AmiTech-Maximem-CPU-Adapter/_autosave-AmiTech-Maximem.pro Normal file
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update=22/05/2015 07:44:53
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2626
AmiTech-Maximem-CPU-Adapter/fp-info-cache Normal file
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AmiTech-Maximem-CPU-Adapter/fp-lib-table Normal file
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3
AmiTech-Maximem-CPU-Adapter/sym-lib-table Normal file
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79
AmiTech-Maximem.pretty/DIP-64_W25.4mm_Socket_LongPads_noSilk.kicad_mod Normal file
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