diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..367af15
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,3 @@
+
+*.sch-bak
+*.kicad_pcb-bak
diff --git a/Gerber/UNTESTET_RCEU2364-C128-64KB-VRAM_V1.1.zip b/Gerber/UNTESTET_RCEU2364-C128-64KB-VRAM_V1.1.zip
deleted file mode 100644
index 17eeab7..0000000
Binary files a/Gerber/UNTESTET_RCEU2364-C128-64KB-VRAM_V1.1.zip and /dev/null differ
diff --git a/Schematic/C128-VRAM-64K-Expansion-cache.lib b/Schematic/C128-VRAM-64K-Expansion-cache.lib
new file mode 100644
index 0000000..80d9471
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion-cache.lib
@@ -0,0 +1,213 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# C128-VRAM-64K-Expansion-rescue_41464C-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF C128-VRAM-64K-Expansion-rescue_41464C-C128-VRAM-64K-Expansion-eagle-import IC 0 40 Y Y 1 L N
+F0 "IC" -300 625 59 H V L BNN
+F1 "C128-VRAM-64K-Expansion-rescue_41464C-C128-VRAM-64K-Expansion-eagle-import" -300 -900 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 1 0 0 -300 -800 -300 600 N
+P 2 1 0 0 -300 -800 400 -800 N
+P 2 1 0 0 400 600 -300 600 N
+P 2 1 0 0 400 600 400 -800 N
+X ~OE 1 -500 -500 200 R 50 50 1 0 I
+X A7 10 -500 -200 200 R 50 50 1 0 I
+X A3 11 -500 200 200 R 50 50 1 0 I
+X A2 12 -500 300 200 R 50 50 1 0 I
+X A1 13 -500 400 200 R 50 50 1 0 I
+X A0 14 -500 500 200 R 50 50 1 0 I
+X I/O3 15 600 300 200 L 50 50 1 0 B
+X ~CAS 16 -500 -600 200 R 50 50 1 0 I
+X I/O4 17 600 200 200 L 50 50 1 0 B
+X GND 18 600 -700 200 L 50 50 1 0 W
+X I/O1 2 600 500 200 L 50 50 1 0 B
+X I/O2 3 600 400 200 L 50 50 1 0 B
+X ~WE 4 -500 -400 200 R 50 50 1 0 I
+X ~RAS 5 -500 -700 200 R 50 50 1 0 I
+X A6 6 -500 -100 200 R 50 50 1 0 I
+X A5 7 -500 0 200 R 50 50 1 0 I
+X A4 8 -500 100 200 R 50 50 1 0 I
+X VCC 9 600 -300 200 L 50 50 1 0 W
+ENDDRAW
+ENDDEF
+#
+# C128-VRAM-64K-Expansion-rescue_C5_2.5-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF C128-VRAM-64K-Expansion-rescue_C5_2.5-C128-VRAM-64K-Expansion-eagle-import C 0 40 Y Y 1 L N
+F0 "C" 60 15 59 H V L BNN
+F1 "C128-VRAM-64K-Expansion-rescue_C5_2.5-C128-VRAM-64K-Expansion-eagle-import" 60 -185 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -80 -80 80 -60 1 0 0 F
+S -80 -40 80 -20 1 0 0 F
+P 2 1 0 0 0 -100 0 -80 N
+P 2 1 0 0 0 0 0 -20 N
+X 1 1 0 100 100 D 0 0 1 0 P
+X 2 2 0 -200 100 U 0 0 1 0 P
+ENDDRAW
+ENDDEF
+#
+# C128-VRAM-64K-Expansion-rescue_DIL48-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF C128-VRAM-64K-Expansion-rescue_DIL48-C128-VRAM-64K-Expansion-eagle-import IC 0 40 Y Y 1 L N
+F0 "IC" -175 1175 59 H V L BNN
+F1 "C128-VRAM-64K-Expansion-rescue_DIL48-C128-VRAM-64K-Expansion-eagle-import" -175 -1350 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A 0 1150 100 -1799 -1 1 0 10 N -100 1150 100 1150
+P 2 1 0 0 -200 -1250 200 -1250 N
+P 2 1 0 0 -200 1150 -200 -1250 N
+P 2 1 0 0 -200 1150 -100 1150 N
+P 2 1 0 0 200 -1250 200 1150 N
+P 2 1 0 0 200 1150 100 1150 N
+X 1 1 -300 1100 100 R 50 0 1 0 P
+X 10 10 -300 200 100 R 50 0 1 0 P
+X 11 11 -300 100 100 R 50 0 1 0 P
+X 12 12 -300 0 100 R 50 0 1 0 P
+X 13 13 -300 -100 100 R 50 0 1 0 P
+X 14 14 -300 -200 100 R 50 0 1 0 P
+X 15 15 -300 -300 100 R 50 0 1 0 P
+X 16 16 -300 -400 100 R 50 0 1 0 P
+X 17 17 -300 -500 100 R 50 0 1 0 P
+X 18 18 -300 -600 100 R 50 0 1 0 P
+X 19 19 -300 -700 100 R 50 0 1 0 P
+X 2 2 -300 1000 100 R 50 0 1 0 P
+X 20 20 -300 -800 100 R 50 0 1 0 P
+X 21 21 -300 -900 100 R 50 0 1 0 P
+X 22 22 -300 -1000 100 R 50 0 1 0 P
+X 23 23 -300 -1100 100 R 50 0 1 0 P
+X 24 24 -300 -1200 100 R 50 0 1 0 P
+X 25 25 300 -1200 100 L 50 0 1 0 P
+X 26 26 300 -1100 100 L 50 0 1 0 P
+X 27 27 300 -1000 100 L 50 0 1 0 P
+X 28 28 300 -900 100 L 50 0 1 0 P
+X 29 29 300 -800 100 L 50 0 1 0 P
+X 3 3 -300 900 100 R 50 0 1 0 P
+X 30 30 300 -700 100 L 50 0 1 0 P
+X 31 31 300 -600 100 L 50 0 1 0 P
+X 32 32 300 -500 100 L 50 0 1 0 P
+X 33 33 300 -400 100 L 50 0 1 0 P
+X 34 34 300 -300 100 L 50 0 1 0 P
+X 35 35 300 -200 100 L 50 0 1 0 P
+X 36 36 300 -100 100 L 50 0 1 0 P
+X 37 37 300 0 100 L 50 0 1 0 P
+X 38 38 300 100 100 L 50 0 1 0 P
+X 39 39 300 200 100 L 50 0 1 0 P
+X 4 4 -300 800 100 R 50 0 1 0 P
+X 40 40 300 300 100 L 50 0 1 0 P
+X 41 41 300 400 100 L 50 0 1 0 P
+X 42 42 300 500 100 L 50 0 1 0 P
+X 43 43 300 600 100 L 50 0 1 0 P
+X 44 44 300 700 100 L 50 0 1 0 P
+X 45 45 300 800 100 L 50 0 1 0 P
+X 46 46 300 900 100 L 50 0 1 0 P
+X 47 47 300 1000 100 L 50 0 1 0 P
+X 48 48 300 1100 100 L 50 0 1 0 P
+X 5 5 -300 700 100 R 50 0 1 0 P
+X 6 6 -300 600 100 R 50 0 1 0 P
+X 7 7 -300 500 100 R 50 0 1 0 P
+X 8 8 -300 400 100 R 50 0 1 0 P
+X 9 9 -300 300 100 R 50 0 1 0 P
+ENDDRAW
+ENDDEF
+#
+# C128-VRAM-64K-Expansion-rescue_GND-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF C128-VRAM-64K-Expansion-rescue_GND-C128-VRAM-64K-Expansion-eagle-import #GND 0 40 Y Y 1 L P
+F0 "#GND" 0 0 50 H I C CNN
+F1 "C128-VRAM-64K-Expansion-rescue_GND-C128-VRAM-64K-Expansion-eagle-import" -100 -100 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 1 0 0 -75 0 75 0 N
+X GND 1 0 100 100 D 0 0 1 0 W
+ENDDRAW
+ENDDEF
+#
+# C128-VRAM-64K-Expansion-rescue_MOS8563-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF C128-VRAM-64K-Expansion-rescue_MOS8563-C128-VRAM-64K-Expansion-eagle-import IC 0 40 Y Y 1 L N
+F0 "IC" -375 1175 59 H V L BNN
+F1 "C128-VRAM-64K-Expansion-rescue_MOS8563-C128-VRAM-64K-Expansion-eagle-import" -375 -1350 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A 50 1150 110 -1799 -1 1 0 10 N -60 1150 160 1150
+T 0 -310 670 51 0 1 0 N/C Normal 0 L B
+P 2 1 0 0 -400 -1250 500 -1250 N
+P 2 1 0 0 -400 1150 -400 -1250 N
+P 2 1 0 0 -400 1150 -300 1150 N
+P 2 1 0 0 -300 1150 -60 1150 N
+P 2 1 0 0 400 1150 160 1150 N
+P 2 1 0 0 500 -1250 500 1150 N
+P 2 1 0 0 500 1150 400 1150 N
+X CCLK 1 -500 1100 100 R 50 50 1 0 P
+X D7 10 -500 200 100 R 50 50 1 0 P
+X D6 11 -500 100 100 R 50 50 1 0 P
+X VSS 12 -500 0 100 R 50 50 1 0 P
+X D5 13 -500 -100 100 R 50 50 1 0 P
+X D4 14 -500 -200 100 R 50 50 1 0 P
+X D3 15 -500 -300 100 R 50 50 1 0 P
+X D2 16 -500 -400 100 R 50 50 1 0 P
+X D1 17 -500 -500 100 R 50 50 1 0 P
+X D0 18 -500 -600 100 R 50 50 1 0 P
+X DISPEN 19 -500 -700 100 R 50 50 1 0 P
+X ~DCLK 2 -500 1000 100 R 50 50 1 0 P
+X VSYNC 20 -500 -800 100 R 50 50 1 0 P
+X DR/~W 21 -500 -900 100 R 50 50 1 0 P
+X INIT 22 -500 -1000 100 R 50 50 1 0 P
+X ~RES 23 -500 -1100 100 R 50 50 1 0 P
+X TEST 24 -500 -1200 100 R 50 50 1 0 P
+X LPEN 25 600 -1200 100 L 50 50 1 0 P
+X DA0 26 600 -1100 100 L 50 50 1 0 P
+X DA1 27 600 -1000 100 L 50 50 1 0 P
+X DA2 28 600 -900 100 L 50 50 1 0 P
+X DA3 29 600 -800 100 L 50 50 1 0 P
+X HSYNC 3 -500 900 100 R 50 50 1 0 P
+X DA4 30 600 -700 100 L 50 50 1 0 P
+X DA5 31 600 -600 100 L 50 50 1 0 P
+X DA6 32 600 -500 100 L 50 50 1 0 P
+X DA7 33 600 -400 100 L 50 50 1 0 P
+X DD0 34 600 -300 100 L 50 50 1 0 P
+X DD1 35 600 -200 100 L 50 50 1 0 P
+X DD2 36 600 -100 100 L 50 50 1 0 P
+X VDD 37 600 0 100 L 50 50 1 0 P
+X DD3 38 600 100 100 L 50 50 1 0 P
+X DD4 39 600 200 100 L 50 50 1 0 P
+X CS 4 -500 800 100 R 50 50 1 0 P
+X DD5 40 600 300 100 L 50 50 1 0 P
+X DD6 41 600 400 100 L 50 50 1 0 P
+X DD7 42 600 500 100 L 50 50 1 0 P
+X I 43 600 600 100 L 50 50 1 0 P
+X B 44 600 700 100 L 50 50 1 0 P
+X G 45 600 800 100 L 50 50 1 0 P
+X R 46 600 900 100 L 50 50 1 0 P
+X ~RAS 47 600 1000 100 L 50 50 1 0 P
+X ~CAS 48 600 1100 100 L 50 50 1 0 P
+X NC 5 -500 700 100 R 50 0 1 0 N
+X N/C 6 -500 600 100 R 50 50 1 0 N
+X ~CS 7 -500 500 100 R 50 50 1 0 P
+X ~RS 8 -500 400 100 R 50 50 1 0 P
+X R/~W 9 -500 300 100 R 50 50 1 0 P
+ENDDRAW
+ENDDEF
+#
+# C128-VRAM-64K-Expansion-rescue_VCC-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF C128-VRAM-64K-Expansion-rescue_VCC-C128-VRAM-64K-Expansion-eagle-import #SUPPLY 0 40 Y Y 1 L P
+F0 "#SUPPLY" 0 0 50 H I C CNN
+F1 "C128-VRAM-64K-Expansion-rescue_VCC-C128-VRAM-64K-Expansion-eagle-import" -75 125 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 50 50 1 0 10 N
+X VCC 1 0 -100 100 U 0 0 1 0 W
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Schematic/C128-VRAM-64K-Expansion-rescue.dcm b/Schematic/C128-VRAM-64K-Expansion-rescue.dcm
new file mode 100644
index 0000000..5f3ed79
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion-rescue.dcm
@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library
diff --git a/Schematic/C128-VRAM-64K-Expansion-rescue.lib b/Schematic/C128-VRAM-64K-Expansion-rescue.lib
new file mode 100644
index 0000000..6dd51d6
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion-rescue.lib
@@ -0,0 +1,244 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# 41464C-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF 41464C-C128-VRAM-64K-Expansion-eagle-import IC 0 40 Y Y 1 L N
+F0 "IC" -300 625 59 H V L BNN
+F1 "41464C-C128-VRAM-64K-Expansion-eagle-import" -300 -900 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 1 0 0 -300 -800 -300 600 N
+P 2 1 0 0 -300 -800 400 -800 N
+P 2 1 0 0 400 600 -300 600 N
+P 2 1 0 0 400 600 400 -800 N
+X ~OE 1 -500 -500 200 R 50 50 1 0 I
+X A7 10 -500 -200 200 R 50 50 1 0 I
+X A3 11 -500 200 200 R 50 50 1 0 I
+X A2 12 -500 300 200 R 50 50 1 0 I
+X A1 13 -500 400 200 R 50 50 1 0 I
+X A0 14 -500 500 200 R 50 50 1 0 I
+X I/O3 15 600 300 200 L 50 50 1 0 B
+X ~CAS 16 -500 -600 200 R 50 50 1 0 I
+X I/O4 17 600 200 200 L 50 50 1 0 B
+X GND 18 600 -700 200 L 50 50 1 0 W
+X I/O1 2 600 500 200 L 50 50 1 0 B
+X I/O2 3 600 400 200 L 50 50 1 0 B
+X ~WE 4 -500 -400 200 R 50 50 1 0 I
+X ~RAS 5 -500 -700 200 R 50 50 1 0 I
+X A6 6 -500 -100 200 R 50 50 1 0 I
+X A5 7 -500 0 200 R 50 50 1 0 I
+X A4 8 -500 100 200 R 50 50 1 0 I
+X VCC 9 600 -300 200 L 50 50 1 0 W
+ENDDRAW
+ENDDEF
+#
+# A4L-LOC-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF A4L-LOC-C128-VRAM-64K-Expansion-eagle-import #FRAME 0 40 Y Y 1 L N
+F0 "#FRAME" 0 0 50 H I C CNN
+F1 "A4L-LOC-C128-VRAM-64K-Expansion-eagle-import" 0 0 50 H I C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+T 0 8550 600 85 0 1 0 >DRAWING_NAME Normal 0 L B
+T 0 8550 400 76 0 1 0 >LAST_DATE_TIME Normal 0 L B
+T 0 9075 200 85 0 1 0 >SHEET Normal 0 L B
+T 0 8540 195 85 0 1 0 Sheet: Normal 0 L B
+P 2 1 0 0 6350 150 6350 950 N
+P 2 1 0 0 6350 950 8475 950 N
+P 2 1 0 0 8475 350 8475 150 N
+P 2 1 0 0 8475 350 8475 550 N
+P 2 1 0 0 8475 550 8475 750 N
+P 2 1 0 0 8475 550 10100 550 N
+P 2 1 0 0 8475 750 8475 950 N
+P 2 1 0 0 8475 750 10100 750 N
+P 2 1 0 0 8475 950 10100 950 N
+P 2 1 0 0 9700 150 9700 350 N
+P 2 1 0 0 9700 350 8475 350 N
+P 2 1 0 0 9700 350 10100 350 N
+P 2 1 0 0 10100 150 10100 350 N
+P 2 1 0 0 10100 350 10100 550 N
+P 2 1 0 0 10100 550 10100 750 N
+P 2 1 0 0 10100 750 10100 950 N
+ENDDRAW
+ENDDEF
+#
+# C5_2.5-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF C5_2.5-C128-VRAM-64K-Expansion-eagle-import C 0 40 Y Y 1 L N
+F0 "C" 60 15 59 H V L BNN
+F1 "C5_2.5-C128-VRAM-64K-Expansion-eagle-import" 60 -185 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -80 -80 80 -60 1 0 0 F
+S -80 -40 80 -20 1 0 0 F
+P 2 1 0 0 0 -100 0 -80 N
+P 2 1 0 0 0 0 0 -20 N
+X 1 1 0 100 100 D 0 0 1 0 P
+X 2 2 0 -200 100 U 0 0 1 0 P
+ENDDRAW
+ENDDEF
+#
+# DIL48-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF DIL48-C128-VRAM-64K-Expansion-eagle-import IC 0 40 Y Y 1 L N
+F0 "IC" -175 1175 59 H V L BNN
+F1 "DIL48-C128-VRAM-64K-Expansion-eagle-import" -175 -1350 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A 0 1150 100 -1799 -1 1 0 10 N -100 1150 100 1150
+P 2 1 0 0 -200 -1250 200 -1250 N
+P 2 1 0 0 -200 1150 -200 -1250 N
+P 2 1 0 0 -200 1150 -100 1150 N
+P 2 1 0 0 200 -1250 200 1150 N
+P 2 1 0 0 200 1150 100 1150 N
+X 1 1 -300 1100 100 R 50 0 1 0 P
+X 10 10 -300 200 100 R 50 0 1 0 P
+X 11 11 -300 100 100 R 50 0 1 0 P
+X 12 12 -300 0 100 R 50 0 1 0 P
+X 13 13 -300 -100 100 R 50 0 1 0 P
+X 14 14 -300 -200 100 R 50 0 1 0 P
+X 15 15 -300 -300 100 R 50 0 1 0 P
+X 16 16 -300 -400 100 R 50 0 1 0 P
+X 17 17 -300 -500 100 R 50 0 1 0 P
+X 18 18 -300 -600 100 R 50 0 1 0 P
+X 19 19 -300 -700 100 R 50 0 1 0 P
+X 2 2 -300 1000 100 R 50 0 1 0 P
+X 20 20 -300 -800 100 R 50 0 1 0 P
+X 21 21 -300 -900 100 R 50 0 1 0 P
+X 22 22 -300 -1000 100 R 50 0 1 0 P
+X 23 23 -300 -1100 100 R 50 0 1 0 P
+X 24 24 -300 -1200 100 R 50 0 1 0 P
+X 25 25 300 -1200 100 L 50 0 1 0 P
+X 26 26 300 -1100 100 L 50 0 1 0 P
+X 27 27 300 -1000 100 L 50 0 1 0 P
+X 28 28 300 -900 100 L 50 0 1 0 P
+X 29 29 300 -800 100 L 50 0 1 0 P
+X 3 3 -300 900 100 R 50 0 1 0 P
+X 30 30 300 -700 100 L 50 0 1 0 P
+X 31 31 300 -600 100 L 50 0 1 0 P
+X 32 32 300 -500 100 L 50 0 1 0 P
+X 33 33 300 -400 100 L 50 0 1 0 P
+X 34 34 300 -300 100 L 50 0 1 0 P
+X 35 35 300 -200 100 L 50 0 1 0 P
+X 36 36 300 -100 100 L 50 0 1 0 P
+X 37 37 300 0 100 L 50 0 1 0 P
+X 38 38 300 100 100 L 50 0 1 0 P
+X 39 39 300 200 100 L 50 0 1 0 P
+X 4 4 -300 800 100 R 50 0 1 0 P
+X 40 40 300 300 100 L 50 0 1 0 P
+X 41 41 300 400 100 L 50 0 1 0 P
+X 42 42 300 500 100 L 50 0 1 0 P
+X 43 43 300 600 100 L 50 0 1 0 P
+X 44 44 300 700 100 L 50 0 1 0 P
+X 45 45 300 800 100 L 50 0 1 0 P
+X 46 46 300 900 100 L 50 0 1 0 P
+X 47 47 300 1000 100 L 50 0 1 0 P
+X 48 48 300 1100 100 L 50 0 1 0 P
+X 5 5 -300 700 100 R 50 0 1 0 P
+X 6 6 -300 600 100 R 50 0 1 0 P
+X 7 7 -300 500 100 R 50 0 1 0 P
+X 8 8 -300 400 100 R 50 0 1 0 P
+X 9 9 -300 300 100 R 50 0 1 0 P
+ENDDRAW
+ENDDEF
+#
+# GND-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF GND-C128-VRAM-64K-Expansion-eagle-import #GND 0 40 Y Y 1 L P
+F0 "#GND" 0 0 50 H I C CNN
+F1 "GND-C128-VRAM-64K-Expansion-eagle-import" -100 -100 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 1 0 0 -75 0 75 0 N
+X GND 1 0 100 100 D 0 0 1 0 W
+ENDDRAW
+ENDDEF
+#
+# MOS8563-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF MOS8563-C128-VRAM-64K-Expansion-eagle-import IC 0 40 Y Y 1 L N
+F0 "IC" -375 1175 59 H V L BNN
+F1 "MOS8563-C128-VRAM-64K-Expansion-eagle-import" -375 -1350 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A 50 1150 110 -1799 -1 1 0 10 N -60 1150 160 1150
+T 0 -310 670 51 0 1 0 N/C Normal 0 L B
+P 2 1 0 0 -400 -1250 500 -1250 N
+P 2 1 0 0 -400 1150 -400 -1250 N
+P 2 1 0 0 -400 1150 -300 1150 N
+P 2 1 0 0 -300 1150 -60 1150 N
+P 2 1 0 0 400 1150 160 1150 N
+P 2 1 0 0 500 -1250 500 1150 N
+P 2 1 0 0 500 1150 400 1150 N
+X CCLK 1 -500 1100 100 R 50 50 1 0 P
+X D7 10 -500 200 100 R 50 50 1 0 P
+X D6 11 -500 100 100 R 50 50 1 0 P
+X VSS 12 -500 0 100 R 50 50 1 0 P
+X D5 13 -500 -100 100 R 50 50 1 0 P
+X D4 14 -500 -200 100 R 50 50 1 0 P
+X D3 15 -500 -300 100 R 50 50 1 0 P
+X D2 16 -500 -400 100 R 50 50 1 0 P
+X D1 17 -500 -500 100 R 50 50 1 0 P
+X D0 18 -500 -600 100 R 50 50 1 0 P
+X DISPEN 19 -500 -700 100 R 50 50 1 0 P
+X ~DCLK 2 -500 1000 100 R 50 50 1 0 P
+X VSYNC 20 -500 -800 100 R 50 50 1 0 P
+X DR/~W 21 -500 -900 100 R 50 50 1 0 P
+X INIT 22 -500 -1000 100 R 50 50 1 0 P
+X ~RES 23 -500 -1100 100 R 50 50 1 0 P
+X TEST 24 -500 -1200 100 R 50 50 1 0 P
+X LPEN 25 600 -1200 100 L 50 50 1 0 P
+X DA0 26 600 -1100 100 L 50 50 1 0 P
+X DA1 27 600 -1000 100 L 50 50 1 0 P
+X DA2 28 600 -900 100 L 50 50 1 0 P
+X DA3 29 600 -800 100 L 50 50 1 0 P
+X HSYNC 3 -500 900 100 R 50 50 1 0 P
+X DA4 30 600 -700 100 L 50 50 1 0 P
+X DA5 31 600 -600 100 L 50 50 1 0 P
+X DA6 32 600 -500 100 L 50 50 1 0 P
+X DA7 33 600 -400 100 L 50 50 1 0 P
+X DD0 34 600 -300 100 L 50 50 1 0 P
+X DD1 35 600 -200 100 L 50 50 1 0 P
+X DD2 36 600 -100 100 L 50 50 1 0 P
+X VDD 37 600 0 100 L 50 50 1 0 P
+X DD3 38 600 100 100 L 50 50 1 0 P
+X DD4 39 600 200 100 L 50 50 1 0 P
+X CS 4 -500 800 100 R 50 50 1 0 P
+X DD5 40 600 300 100 L 50 50 1 0 P
+X DD6 41 600 400 100 L 50 50 1 0 P
+X DD7 42 600 500 100 L 50 50 1 0 P
+X I 43 600 600 100 L 50 50 1 0 P
+X B 44 600 700 100 L 50 50 1 0 P
+X G 45 600 800 100 L 50 50 1 0 P
+X R 46 600 900 100 L 50 50 1 0 P
+X ~RAS 47 600 1000 100 L 50 50 1 0 P
+X ~CAS 48 600 1100 100 L 50 50 1 0 P
+X NC 5 -500 700 100 R 50 0 1 0 N
+X N/C 6 -500 600 100 R 50 50 1 0 N
+X ~CS 7 -500 500 100 R 50 50 1 0 P
+X ~RS 8 -500 400 100 R 50 50 1 0 P
+X R/~W 9 -500 300 100 R 50 50 1 0 P
+ENDDRAW
+ENDDEF
+#
+# VCC-C128-VRAM-64K-Expansion-eagle-import
+#
+DEF VCC-C128-VRAM-64K-Expansion-eagle-import #SUPPLY 0 40 Y Y 1 L P
+F0 "#SUPPLY" 0 0 50 H I C CNN
+F1 "VCC-C128-VRAM-64K-Expansion-eagle-import" -75 125 59 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 50 50 1 0 10 N
+X VCC 1 0 -100 100 U 0 0 1 0 W
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Schematic/C128-VRAM-64K-Expansion.kicad_pcb b/Schematic/C128-VRAM-64K-Expansion.kicad_pcb
new file mode 100644
index 0000000..c9f5cb2
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion.kicad_pcb
@@ -0,0 +1,1470 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.8)-1")
+
+  (general
+    (thickness 1.6)
+    (drawings 16)
+    (tracks 228)
+    (zones 0)
+    (modules 5)
+    (nets 57)
+  )
+
+  (page A4)
+  (title_block
+    (title "RCEU2364 C128 64KB VRAM")
+    (date 2021-02-03)
+    (rev v1.2)
+    (company https://retro-commodore.eu)
+    (comment 3 "Copyright (c) 2018-2021")
+    (comment 4 "by Tomse")
+  )
+
+  (layers
+    (0 Top signal)
+    (31 Bottom signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.1524)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.1524)
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+    (uvias_allowed no)
+    (uvia_min_size 0.2)
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+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 0 0)
+    (visible_elements 7FFFFFFF)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "../Gerber/RCEU2364-C128-64KB-VRAM_V1.2/"))
+  )
+
+  (net 0 "")
+  (net 1 VCC)
+  (net 2 GND)
+  (net 3 /~CAS)
+  (net 4 /~RAS)
+  (net 5 /R)
+  (net 6 /G)
+  (net 7 /B)
+  (net 8 /I)
+  (net 9 /DD2)
+  (net 10 /DA7)
+  (net 11 /DA6)
+  (net 12 /DA5)
+  (net 13 /DA4)
+  (net 14 /DA3)
+  (net 15 /DA2)
+  (net 16 /DA1)
+  (net 17 /DA0)
+  (net 18 /LPEN)
+  (net 19 /TEST)
+  (net 20 /~RES)
+  (net 21 /INIT)
+  (net 22 /DR/~W)
+  (net 23 /VSYNC)
+  (net 24 /DISPEN)
+  (net 25 /D0)
+  (net 26 /D1)
+  (net 27 /D2)
+  (net 28 /D3)
+  (net 29 /D4)
+  (net 30 /D5)
+  (net 31 /D6)
+  (net 32 /D7)
+  (net 33 /R/~W)
+  (net 34 /~RS)
+  (net 35 /~CS)
+  (net 36 /N/C)
+  (net 37 /NC)
+  (net 38 /CS)
+  (net 39 /HSYNC)
+  (net 40 /~DCLK)
+  (net 41 /CCLK)
+  (net 42 "Net-(IC2-Pad42)")
+  (net 43 "Net-(IC2-Pad41)")
+  (net 44 "Net-(IC2-Pad40)")
+  (net 45 "Net-(IC2-Pad39)")
+  (net 46 "Net-(IC2-Pad38)")
+  (net 47 "Net-(IC2-Pad36)")
+  (net 48 "Net-(IC2-Pad35)")
+  (net 49 "Net-(IC2-Pad34)")
+  (net 50 /DD7)
+  (net 51 /DD6)
+  (net 52 /DD5)
+  (net 53 /DD4)
+  (net 54 /DD3)
+  (net 55 /DD1)
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+    (add_net /B)
+    (add_net /CCLK)
+    (add_net /CS)
+    (add_net /D0)
+    (add_net /D1)
+    (add_net /D2)
+    (add_net /D3)
+    (add_net /D4)
+    (add_net /D5)
+    (add_net /D6)
+    (add_net /D7)
+    (add_net /DA0)
+    (add_net /DA1)
+    (add_net /DA2)
+    (add_net /DA3)
+    (add_net /DA4)
+    (add_net /DA5)
+    (add_net /DA6)
+    (add_net /DA7)
+    (add_net /DD0)
+    (add_net /DD1)
+    (add_net /DD2)
+    (add_net /DD3)
+    (add_net /DD4)
+    (add_net /DD5)
+    (add_net /DD6)
+    (add_net /DD7)
+    (add_net /DISPEN)
+    (add_net /DR/~W)
+    (add_net /G)
+    (add_net /HSYNC)
+    (add_net /I)
+    (add_net /INIT)
+    (add_net /LPEN)
+    (add_net /N/C)
+    (add_net /NC)
+    (add_net /R)
+    (add_net /R/~W)
+    (add_net /TEST)
+    (add_net /VSYNC)
+    (add_net /~CAS)
+    (add_net /~CS)
+    (add_net /~DCLK)
+    (add_net /~RAS)
+    (add_net /~RES)
+    (add_net /~RS)
+    (add_net "Net-(IC2-Pad34)")
+    (add_net "Net-(IC2-Pad35)")
+    (add_net "Net-(IC2-Pad36)")
+    (add_net "Net-(IC2-Pad38)")
+    (add_net "Net-(IC2-Pad39)")
+    (add_net "Net-(IC2-Pad40)")
+    (add_net "Net-(IC2-Pad41)")
+    (add_net "Net-(IC2-Pad42)")
+  )
+
+  (net_class Power ""
+    (clearance 0.1524)
+    (trace_width 0.5)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net GND)
+    (add_net VCC)
+  )
+
+  (module C128-VRAM-64K-Expansion:MOS8563 (layer Top) (tedit 0) (tstamp 5FD29BA5)
+    (at 138.5 105 270)
+    (descr "<b>Dual In Line Package</b>")
+    (path /22F7723E)
+    (fp_text reference IC1 (at -24.2536 0.12 270) (layer F.SilkS) hide
+      (effects (font (size 1.6891 1.6891) (thickness 0.16891)) (justify left bottom))
+    )
+    (fp_text value MOS8563 (at -23.25 2.5 270 unlocked) (layer F.SilkS)
+      (effects (font (size 1.6891 1.6891) (thickness 0.16891)) (justify left bottom))
+    )
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+    (fp_line (start -29.845 -6.604) (end -29.845 -0.889) (layer F.SilkS) (width 0.1524))
+    (fp_line (start 29.845 -6.604) (end -29.845 -6.604) (layer F.SilkS) (width 0.1524))
+    (fp_line (start 29.845 6.604) (end 29.845 -6.604) (layer F.SilkS) (width 0.1524))
+    (fp_line (start -29.845 6.604) (end 29.845 6.604) (layer F.SilkS) (width 0.1524))
+    (fp_arc (start -29.845 0.127) (end -29.845 -0.889) (angle 180) (layer F.SilkS) (width 0.1524))
+    (pad 48 thru_hole oval (at -29.21 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 3 /~CAS) (solder_mask_margin 0.1016))
+    (pad 47 thru_hole oval (at -26.67 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 4 /~RAS) (solder_mask_margin 0.1016))
+    (pad 46 thru_hole oval (at -24.13 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 5 /R) (solder_mask_margin 0.1016))
+    (pad 45 thru_hole oval (at -21.59 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 6 /G) (solder_mask_margin 0.1016))
+    (pad 44 thru_hole oval (at -19.05 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 7 /B) (solder_mask_margin 0.1016))
+    (pad 43 thru_hole oval (at -16.51 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 8 /I) (solder_mask_margin 0.1016))
+    (pad 42 thru_hole oval (at -13.97 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 50 /DD7) (solder_mask_margin 0.1016))
+    (pad 41 thru_hole oval (at -11.43 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 51 /DD6) (solder_mask_margin 0.1016))
+    (pad 40 thru_hole oval (at -8.89 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 52 /DD5) (solder_mask_margin 0.1016))
+    (pad 39 thru_hole oval (at -6.35 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 53 /DD4) (solder_mask_margin 0.1016))
+    (pad 38 thru_hole oval (at -3.81 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 54 /DD3) (solder_mask_margin 0.1016))
+    (pad 37 thru_hole oval (at -1.27 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 1 VCC) (solder_mask_margin 0.1016))
+    (pad 36 thru_hole oval (at 1.27 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 9 /DD2) (solder_mask_margin 0.1016))
+    (pad 35 thru_hole oval (at 3.81 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 55 /DD1) (solder_mask_margin 0.1016))
+    (pad 34 thru_hole oval (at 6.35 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 56 /DD0) (solder_mask_margin 0.1016))
+    (pad 33 thru_hole oval (at 8.89 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 10 /DA7) (solder_mask_margin 0.1016))
+    (pad 32 thru_hole oval (at 11.43 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 11 /DA6) (solder_mask_margin 0.1016))
+    (pad 31 thru_hole oval (at 13.97 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 12 /DA5) (solder_mask_margin 0.1016))
+    (pad 30 thru_hole oval (at 16.51 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 13 /DA4) (solder_mask_margin 0.1016))
+    (pad 29 thru_hole oval (at 19.05 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 14 /DA3) (solder_mask_margin 0.1016))
+    (pad 28 thru_hole oval (at 21.59 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 15 /DA2) (solder_mask_margin 0.1016))
+    (pad 27 thru_hole oval (at 24.13 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 16 /DA1) (solder_mask_margin 0.1016))
+    (pad 26 thru_hole oval (at 26.67 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 17 /DA0) (solder_mask_margin 0.1016))
+    (pad 25 thru_hole oval (at 29.21 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 18 /LPEN) (solder_mask_margin 0.1016))
+    (pad 24 thru_hole oval (at 29.21 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 19 /TEST) (solder_mask_margin 0.1016))
+    (pad 23 thru_hole oval (at 26.67 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 20 /~RES) (solder_mask_margin 0.1016))
+    (pad 22 thru_hole oval (at 24.13 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 21 /INIT) (solder_mask_margin 0.1016))
+    (pad 21 thru_hole oval (at 21.59 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 22 /DR/~W) (solder_mask_margin 0.1016))
+    (pad 20 thru_hole oval (at 19.05 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 23 /VSYNC) (solder_mask_margin 0.1016))
+    (pad 19 thru_hole oval (at 16.51 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 24 /DISPEN) (solder_mask_margin 0.1016))
+    (pad 18 thru_hole oval (at 13.97 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 25 /D0) (solder_mask_margin 0.1016))
+    (pad 17 thru_hole oval (at 11.43 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 26 /D1) (solder_mask_margin 0.1016))
+    (pad 16 thru_hole oval (at 8.89 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 27 /D2) (solder_mask_margin 0.1016))
+    (pad 15 thru_hole oval (at 6.35 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 28 /D3) (solder_mask_margin 0.1016))
+    (pad 14 thru_hole oval (at 3.81 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 29 /D4) (solder_mask_margin 0.1016))
+    (pad 13 thru_hole oval (at 1.27 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 30 /D5) (solder_mask_margin 0.1016))
+    (pad 12 thru_hole oval (at -1.27 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 2 GND) (solder_mask_margin 0.1016))
+    (pad 11 thru_hole oval (at -3.81 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 31 /D6) (solder_mask_margin 0.1016))
+    (pad 10 thru_hole oval (at -6.35 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 32 /D7) (solder_mask_margin 0.1016))
+    (pad 9 thru_hole oval (at -8.89 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 33 /R/~W) (solder_mask_margin 0.1016))
+    (pad 8 thru_hole oval (at -11.43 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 34 /~RS) (solder_mask_margin 0.1016))
+    (pad 7 thru_hole oval (at -13.97 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 35 /~CS) (solder_mask_margin 0.1016))
+    (pad 6 thru_hole oval (at -16.51 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 36 /N/C) (solder_mask_margin 0.1016))
+    (pad 5 thru_hole oval (at -19.05 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 37 /NC) (solder_mask_margin 0.1016))
+    (pad 4 thru_hole oval (at -21.59 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 38 /CS) (solder_mask_margin 0.1016))
+    (pad 3 thru_hole oval (at -24.13 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 39 /HSYNC) (solder_mask_margin 0.1016))
+    (pad 2 thru_hole oval (at -26.67 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 40 /~DCLK) (solder_mask_margin 0.1016))
+    (pad 1 thru_hole oval (at -29.21 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 41 /CCLK) (solder_mask_margin 0.1016))
+    (model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-48_W15.24mm_Socket.step
+      (offset (xyz -29.2 -7.6 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 -90))
+    )
+  )
+
+  (module C128-VRAM-64K-Expansion:DIL48 (layer Top) (tedit 5FD29BDE) (tstamp 5FD29BDE)
+    (at 134.75 105.0036 270)
+    (descr "<b>Dual In Line Package</b>")
+    (path /BC34DC86)
+    (fp_text reference IC2 (at -30.226 6.35) (layer F.SilkS) hide
+      (effects (font (size 1.6891 1.6891) (thickness 0.16891)) (justify left bottom))
+    )
+    (fp_text value DIL48 (at -16.637 1.016 270) (layer F.Fab)
+      (effects (font (size 1.6891 1.6891) (thickness 0.16891)) (justify right bottom))
+    )
+    (pad 48 thru_hole oval (at -29.21 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 3 /~CAS) (solder_mask_margin 0.1016))
+    (pad 47 thru_hole oval (at -26.67 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 4 /~RAS) (solder_mask_margin 0.1016))
+    (pad 46 thru_hole oval (at -24.13 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 5 /R) (solder_mask_margin 0.1016))
+    (pad 45 thru_hole oval (at -21.59 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 6 /G) (solder_mask_margin 0.1016))
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+    (pad 43 thru_hole oval (at -16.51 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
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+    (pad 42 thru_hole oval (at -13.97 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 42 "Net-(IC2-Pad42)") (solder_mask_margin 0.1016))
+    (pad 41 thru_hole oval (at -11.43 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 43 "Net-(IC2-Pad41)") (solder_mask_margin 0.1016))
+    (pad 40 thru_hole oval (at -8.89 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
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+    (pad 39 thru_hole oval (at -6.35 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 45 "Net-(IC2-Pad39)") (solder_mask_margin 0.1016))
+    (pad 38 thru_hole oval (at -3.81 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 46 "Net-(IC2-Pad38)") (solder_mask_margin 0.1016))
+    (pad 37 thru_hole oval (at -1.27 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 1 VCC) (solder_mask_margin 0.1016))
+    (pad 36 thru_hole oval (at 1.27 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 47 "Net-(IC2-Pad36)") (solder_mask_margin 0.1016))
+    (pad 35 thru_hole oval (at 3.81 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 48 "Net-(IC2-Pad35)") (solder_mask_margin 0.1016))
+    (pad 34 thru_hole oval (at 6.35 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 49 "Net-(IC2-Pad34)") (solder_mask_margin 0.1016))
+    (pad 33 thru_hole oval (at 8.89 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
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+      (net 12 /DA5) (solder_mask_margin 0.1016))
+    (pad 30 thru_hole oval (at 16.51 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 13 /DA4) (solder_mask_margin 0.1016))
+    (pad 29 thru_hole oval (at 19.05 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 14 /DA3) (solder_mask_margin 0.1016))
+    (pad 28 thru_hole oval (at 21.59 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 15 /DA2) (solder_mask_margin 0.1016))
+    (pad 27 thru_hole oval (at 24.13 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 16 /DA1) (solder_mask_margin 0.1016))
+    (pad 26 thru_hole oval (at 26.67 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 17 /DA0) (solder_mask_margin 0.1016))
+    (pad 25 thru_hole oval (at 29.21 -7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 18 /LPEN) (solder_mask_margin 0.1016))
+    (pad 24 thru_hole oval (at 29.21 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 19 /TEST) (solder_mask_margin 0.1016))
+    (pad 23 thru_hole oval (at 26.67 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 20 /~RES) (solder_mask_margin 0.1016))
+    (pad 22 thru_hole oval (at 24.13 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 21 /INIT) (solder_mask_margin 0.1016))
+    (pad 21 thru_hole oval (at 21.59 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 22 /DR/~W) (solder_mask_margin 0.1016))
+    (pad 20 thru_hole oval (at 19.05 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 23 /VSYNC) (solder_mask_margin 0.1016))
+    (pad 19 thru_hole oval (at 16.51 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 24 /DISPEN) (solder_mask_margin 0.1016))
+    (pad 18 thru_hole oval (at 13.97 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 25 /D0) (solder_mask_margin 0.1016))
+    (pad 17 thru_hole oval (at 11.43 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 26 /D1) (solder_mask_margin 0.1016))
+    (pad 16 thru_hole oval (at 8.89 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 27 /D2) (solder_mask_margin 0.1016))
+    (pad 15 thru_hole oval (at 6.35 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 28 /D3) (solder_mask_margin 0.1016))
+    (pad 14 thru_hole oval (at 3.81 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 29 /D4) (solder_mask_margin 0.1016))
+    (pad 13 thru_hole oval (at 1.27 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 30 /D5) (solder_mask_margin 0.1016))
+    (pad 12 thru_hole oval (at -1.27 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 2 GND) (solder_mask_margin 0.1016))
+    (pad 11 thru_hole oval (at -3.81 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 31 /D6) (solder_mask_margin 0.1016))
+    (pad 10 thru_hole oval (at -6.35 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 32 /D7) (solder_mask_margin 0.1016))
+    (pad 9 thru_hole oval (at -8.89 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 33 /R/~W) (solder_mask_margin 0.1016))
+    (pad 8 thru_hole oval (at -11.43 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 34 /~RS) (solder_mask_margin 0.1016))
+    (pad 7 thru_hole oval (at -13.97 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 35 /~CS) (solder_mask_margin 0.1016))
+    (pad 6 thru_hole oval (at -16.51 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 36 /N/C) (solder_mask_margin 0.1016))
+    (pad 5 thru_hole oval (at -19.05 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 37 /NC) (solder_mask_margin 0.1016))
+    (pad 4 thru_hole oval (at -21.59 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 38 /CS) (solder_mask_margin 0.1016))
+    (pad 3 thru_hole oval (at -24.13 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 39 /HSYNC) (solder_mask_margin 0.1016))
+    (pad 2 thru_hole oval (at -26.67 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 40 /~DCLK) (solder_mask_margin 0.1016))
+    (pad 1 thru_hole oval (at -29.21 7.62) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 41 /CCLK) (solder_mask_margin 0.1016))
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x24_P2.54mm_Vertical.step
+      (offset (xyz -29.2 -7.6 -2))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 -180 -90))
+    )
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x24_P2.54mm_Vertical.step
+      (offset (xyz -29.2 7.6 -2))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 -180 -90))
+    )
+  )
+
+  (module C128-VRAM-64K-Expansion:DIL18 (layer Top) (tedit 0) (tstamp 5FFBEE5C)
+    (at 154.94 122.7836 270)
+    (descr "<b>Dual In Line Package</b>")
+    (path /B686635D)
+    (fp_text reference IC3 (at -11.684 3.048) (layer F.SilkS) hide
+      (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom))
+    )
+    (fp_text value 41464C (at -9.525 0.635 90) (layer F.Fab)
+      (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom))
+    )
+    (fp_line (start -11.43 2.921) (end -11.43 1.016) (layer F.SilkS) (width 0.1524))
+    (fp_line (start -11.43 -2.921) (end -11.43 -1.016) (layer F.SilkS) (width 0.1524))
+    (fp_line (start 11.43 -2.921) (end 11.43 2.921) (layer F.SilkS) (width 0.1524))
+    (fp_line (start -11.43 2.921) (end 11.43 2.921) (layer F.SilkS) (width 0.1524))
+    (fp_line (start 11.43 -2.921) (end -11.43 -2.921) (layer F.SilkS) (width 0.1524))
+    (fp_arc (start -11.43 0) (end -11.43 -1.016) (angle 180) (layer F.SilkS) (width 0.1524))
+    (pad 18 thru_hole oval (at -10.16 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 2 GND) (solder_mask_margin 0.1016))
+    (pad 17 thru_hole oval (at -7.62 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 54 /DD3) (solder_mask_margin 0.1016))
+    (pad 16 thru_hole oval (at -5.08 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 3 /~CAS) (solder_mask_margin 0.1016))
+    (pad 15 thru_hole oval (at -2.54 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 56 /DD0) (solder_mask_margin 0.1016))
+    (pad 14 thru_hole oval (at 0 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 10 /DA7) (solder_mask_margin 0.1016))
+    (pad 13 thru_hole oval (at 2.54 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 11 /DA6) (solder_mask_margin 0.1016))
+    (pad 12 thru_hole oval (at 5.08 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 13 /DA4) (solder_mask_margin 0.1016))
+    (pad 11 thru_hole oval (at 7.62 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 15 /DA2) (solder_mask_margin 0.1016))
+    (pad 10 thru_hole oval (at 10.16 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 17 /DA0) (solder_mask_margin 0.1016))
+    (pad 9 thru_hole oval (at 10.16 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 1 VCC) (solder_mask_margin 0.1016))
+    (pad 5 thru_hole oval (at 0 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 4 /~RAS) (solder_mask_margin 0.1016))
+    (pad 6 thru_hole oval (at 2.54 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 12 /DA5) (solder_mask_margin 0.1016))
+    (pad 4 thru_hole oval (at -2.54 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 22 /DR/~W) (solder_mask_margin 0.1016))
+    (pad 3 thru_hole oval (at -5.08 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 55 /DD1) (solder_mask_margin 0.1016))
+    (pad 8 thru_hole oval (at 7.62 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 16 /DA1) (solder_mask_margin 0.1016))
+    (pad 7 thru_hole oval (at 5.08 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 14 /DA3) (solder_mask_margin 0.1016))
+    (pad 2 thru_hole oval (at -7.62 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 9 /DD2) (solder_mask_margin 0.1016))
+    (pad 1 thru_hole oval (at -10.16 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 2 GND) (solder_mask_margin 0.1016))
+    (model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-18_W7.62mm.step
+      (offset (xyz -10.2 -3.8 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 -90))
+    )
+  )
+
+  (module C128-VRAM-64K-Expansion:C5B2.5 (layer Top) (tedit 0) (tstamp 5FD29B92)
+    (at 160.25 108.5 180)
+    (descr "<B>MKS2</B>, 7.5 x 2.5 mm, grid 5.08 mm")
+    (path /65963FEF)
+    (fp_text reference C1 (at -2.032 -1.524) (layer F.SilkS) hide
+      (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right bottom))
+    )
+    (fp_text value 22nF (at -2.5 1.5) (layer F.SilkS)
+      (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right bottom))
+    )
+    (fp_line (start 3.429 -1.27) (end -3.429 -1.27) (layer F.SilkS) (width 0.1524))
+    (fp_line (start 3.683 1.016) (end 3.683 -1.016) (layer F.SilkS) (width 0.1524))
+    (fp_line (start -3.429 1.27) (end 3.429 1.27) (layer F.SilkS) (width 0.1524))
+    (fp_line (start -3.683 -1.016) (end -3.683 1.016) (layer F.SilkS) (width 0.1524))
+    (fp_line (start 0.3302 0) (end 1.524 0) (layer F.SilkS) (width 0.1524))
+    (fp_line (start 0.3302 0) (end 0.3302 0.635) (layer F.SilkS) (width 0.3048))
+    (fp_line (start 0.3302 -0.635) (end 0.3302 0) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -0.3048 0) (end -1.524 0) (layer F.SilkS) (width 0.1524))
+    (fp_line (start -0.3048 0) (end -0.3048 0.635) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -0.3048 -0.635) (end -0.3048 0) (layer F.SilkS) (width 0.3048))
+    (fp_arc (start -3.429 -1.016) (end -3.683 -1.016) (angle 90) (layer F.SilkS) (width 0.1524))
+    (fp_arc (start -3.429 1.016) (end -3.683 1.016) (angle -90) (layer F.SilkS) (width 0.1524))
+    (fp_arc (start 3.429 1.016) (end 3.429 1.27) (angle -90) (layer F.SilkS) (width 0.1524))
+    (fp_arc (start 3.429 -1.016) (end 3.429 -1.27) (angle 90) (layer F.SilkS) (width 0.1524))
+    (pad 2 thru_hole circle (at 2.54 0 180) (size 1.6002 1.6002) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 2 GND) (solder_mask_margin 0.1016))
+    (pad 1 thru_hole circle (at -2.54 0 180) (size 1.6002 1.6002) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 1 VCC) (solder_mask_margin 0.1016))
+    (model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D4.3mm_W1.9mm_P5.00mm.step
+      (offset (xyz -2.5 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module C128-VRAM-64K-Expansion:DIL18 (layer Top) (tedit 0) (tstamp 5FD29C32)
+    (at 166.37 122.7836 270)
+    (descr "<b>Dual In Line Package</b>")
+    (path /FA55F29D)
+    (fp_text reference IC4 (at -11.684 3.048) (layer F.SilkS) hide
+      (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom))
+    )
+    (fp_text value 41464C (at -9.525 0.635 90) (layer F.Fab)
+      (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom))
+    )
+    (fp_line (start -11.43 2.921) (end -11.43 1.016) (layer F.SilkS) (width 0.1524))
+    (fp_line (start -11.43 -2.921) (end -11.43 -1.016) (layer F.SilkS) (width 0.1524))
+    (fp_line (start 11.43 -2.921) (end 11.43 2.921) (layer F.SilkS) (width 0.1524))
+    (fp_line (start -11.43 2.921) (end 11.43 2.921) (layer F.SilkS) (width 0.1524))
+    (fp_line (start 11.43 -2.921) (end -11.43 -2.921) (layer F.SilkS) (width 0.1524))
+    (fp_arc (start -11.43 0) (end -11.43 -1.016) (angle 180) (layer F.SilkS) (width 0.1524))
+    (pad 18 thru_hole oval (at -10.16 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 2 GND) (solder_mask_margin 0.1016))
+    (pad 17 thru_hole oval (at -7.62 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 50 /DD7) (solder_mask_margin 0.1016))
+    (pad 16 thru_hole oval (at -5.08 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 3 /~CAS) (solder_mask_margin 0.1016))
+    (pad 15 thru_hole oval (at -2.54 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 53 /DD4) (solder_mask_margin 0.1016))
+    (pad 14 thru_hole oval (at 0 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 10 /DA7) (solder_mask_margin 0.1016))
+    (pad 13 thru_hole oval (at 2.54 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 11 /DA6) (solder_mask_margin 0.1016))
+    (pad 12 thru_hole oval (at 5.08 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 13 /DA4) (solder_mask_margin 0.1016))
+    (pad 11 thru_hole oval (at 7.62 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 15 /DA2) (solder_mask_margin 0.1016))
+    (pad 10 thru_hole oval (at 10.16 -3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 17 /DA0) (solder_mask_margin 0.1016))
+    (pad 9 thru_hole oval (at 10.16 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 1 VCC) (solder_mask_margin 0.1016))
+    (pad 5 thru_hole oval (at 0 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 4 /~RAS) (solder_mask_margin 0.1016))
+    (pad 6 thru_hole oval (at 2.54 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 12 /DA5) (solder_mask_margin 0.1016))
+    (pad 4 thru_hole oval (at -2.54 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 22 /DR/~W) (solder_mask_margin 0.1016))
+    (pad 3 thru_hole oval (at -5.08 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 52 /DD5) (solder_mask_margin 0.1016))
+    (pad 8 thru_hole oval (at 7.62 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 16 /DA1) (solder_mask_margin 0.1016))
+    (pad 7 thru_hole oval (at 5.08 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 14 /DA3) (solder_mask_margin 0.1016))
+    (pad 2 thru_hole oval (at -7.62 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 51 /DD6) (solder_mask_margin 0.1016))
+    (pad 1 thru_hole oval (at -10.16 3.81) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+      (net 2 GND) (solder_mask_margin 0.1016))
+    (model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-18_W7.62mm.step
+      (offset (xyz -10.2 -3.8 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 -90))
+    )
+  )
+
+  (gr_text "4464 / 41464" (at 166 123.25 270) (layer F.SilkS) (tstamp 5FFBE749)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (gr_line (start 168.25 105) (end 167.75 105) (layer Edge.Cuts) (width 0.05) (tstamp 5FFB6B46))
+  (gr_line (start 173 109.75) (end 168.25 105) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 171.5 135.5) (end 172 135.5) (layer Edge.Cuts) (width 0.05) (tstamp 5FFB6B45))
+  (gr_arc (start 150 75.25) (end 150.75 75.25) (angle -90) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 125.5 74.5) (end 150 74.5) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 150.75 104.25) (end 150.75 75.25) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 151.5 105) (end 167.75 105) (layer Edge.Cuts) (width 0.05) (tstamp 5FFB6A0D))
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+  (gr_line (start 125.5 135.5) (end 171.5 135.5) (layer Edge.Cuts) (width 0.05) (tstamp 5FFB6A0C))
+  (gr_line (start 124.5 134.5) (end 124.5 75.5) (layer Edge.Cuts) (width 0.05) (tstamp 5FFB6A0B))
+  (gr_arc (start 125.5 134.5) (end 124.5 134.5) (angle -90) (layer Edge.Cuts) (width 0.05))
+  (gr_arc (start 172 134.5) (end 172 135.5) (angle -90) (layer Edge.Cuts) (width 0.05))
+  (gr_arc (start 151.5 104.25) (end 150.75 104.25) (angle -90) (layer Edge.Cuts) (width 0.05))
+  (gr_arc (start 125.5 75.5) (end 125.5 74.5) (angle -90) (layer Edge.Cuts) (width 0.05))
+  (gr_text "RCEU 2364 C128 64KB VRAM\nretro-commodore.eu v1.2\nTaunusAnden Edition" (at 133 114.75 -90) (layer B.SilkS) (tstamp 5FFB59BB)
+    (effects (font (size 1.6891 1.6891) (thickness 0.14224)) (justify left bottom mirror))
+  )
+
+  (segment (start 161.185089 106.895089) (end 162.79 108.5) (width 0.5) (layer Top) (net 1))
+  (segment (start 152.471427 106.895089) (end 161.185089 106.895089) (width 0.5) (layer Top) (net 1))
+  (segment (start 149.725 104.148662) (end 152.471427 106.895089) (width 0.5) (layer Top) (net 1))
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+  (segment (start 145.20656 97.4) (end 147.8 97.4) (width 0.5) (layer Top) (net 1))
+  (segment (start 144.2 98.40656) (end 145.20656 97.4) (width 0.5) (layer Top) (net 1))
+  (segment (start 144.2 103.8) (end 144.2 98.40656) (width 0.5) (layer Top) (net 1))
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diff --git a/Schematic/C128-VRAM-64K-Expansion.pretty/C5B2.5.kicad_mod b/Schematic/C128-VRAM-64K-Expansion.pretty/C5B2.5.kicad_mod
new file mode 100644
index 0000000..15f6923
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion.pretty/C5B2.5.kicad_mod
@@ -0,0 +1,27 @@
+(module C5B2.5 (layer F.Cu) (tedit 0)
+  (descr "<B>MKS2</B>, 7.5 x 2.5 mm, grid 5.08 mm")
+  (fp_text reference C1 (at -2.032 -1.524) (layer F.SilkS)
+    (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom))
+  )
+  (fp_text value 22nF (at -2.032 2.794) (layer F.Fab)
+    (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom))
+  )
+  (fp_line (start -0.3048 -0.635) (end -0.3048 0) (layer F.SilkS) (width 0.3048))
+  (fp_line (start -0.3048 0) (end -0.3048 0.635) (layer F.SilkS) (width 0.3048))
+  (fp_line (start -0.3048 0) (end -1.524 0) (layer F.SilkS) (width 0.1524))
+  (fp_line (start 0.3302 -0.635) (end 0.3302 0) (layer F.SilkS) (width 0.3048))
+  (fp_line (start 0.3302 0) (end 0.3302 0.635) (layer F.SilkS) (width 0.3048))
+  (fp_line (start 0.3302 0) (end 1.524 0) (layer F.SilkS) (width 0.1524))
+  (fp_line (start -3.683 -1.016) (end -3.683 1.016) (layer F.SilkS) (width 0.1524))
+  (fp_line (start -3.429 1.27) (end 3.429 1.27) (layer F.SilkS) (width 0.1524))
+  (fp_line (start 3.683 1.016) (end 3.683 -1.016) (layer F.SilkS) (width 0.1524))
+  (fp_line (start 3.429 -1.27) (end -3.429 -1.27) (layer F.SilkS) (width 0.1524))
+  (fp_arc (start 3.429 -1.016) (end 3.429 -1.27) (angle 90) (layer F.SilkS) (width 0.1524))
+  (fp_arc (start 3.429 1.016) (end 3.429 1.27) (angle -90) (layer F.SilkS) (width 0.1524))
+  (fp_arc (start -3.429 1.016) (end -3.683 1.016) (angle -90) (layer F.SilkS) (width 0.1524))
+  (fp_arc (start -3.429 -1.016) (end -3.683 -1.016) (angle 90) (layer F.SilkS) (width 0.1524))
+  (pad 1 thru_hole circle (at -2.54 0) (size 1.6002 1.6002) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 2 thru_hole circle (at 2.54 0) (size 1.6002 1.6002) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+)
diff --git a/Schematic/C128-VRAM-64K-Expansion.pretty/DIL18.kicad_mod b/Schematic/C128-VRAM-64K-Expansion.pretty/DIL18.kicad_mod
new file mode 100644
index 0000000..a02da82
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion.pretty/DIL18.kicad_mod
@@ -0,0 +1,51 @@
+(module DIL18 (layer F.Cu) (tedit 0)
+  (descr "<b>Dual In Line Package</b>")
+  (fp_text reference IC4 (at -11.684 3.048 -270) (layer F.SilkS)
+    (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom))
+  )
+  (fp_text value "" (at -9.525 0.635 -180) (layer F.Fab)
+    (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom))
+  )
+  (fp_line (start 11.43 -2.921) (end -11.43 -2.921) (layer F.SilkS) (width 0.1524))
+  (fp_line (start -11.43 2.921) (end 11.43 2.921) (layer F.SilkS) (width 0.1524))
+  (fp_line (start 11.43 -2.921) (end 11.43 2.921) (layer F.SilkS) (width 0.1524))
+  (fp_line (start -11.43 -2.921) (end -11.43 -1.016) (layer F.SilkS) (width 0.1524))
+  (fp_line (start -11.43 2.921) (end -11.43 1.016) (layer F.SilkS) (width 0.1524))
+  (fp_arc (start -11.43 0) (end -11.43 -1.016) (angle 180) (layer F.SilkS) (width 0.1524))
+  (pad 1 thru_hole oval (at -10.16 3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 2 thru_hole oval (at -7.62 3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 7 thru_hole oval (at 5.08 3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 8 thru_hole oval (at 7.62 3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 3 thru_hole oval (at -5.08 3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 4 thru_hole oval (at -2.54 3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 6 thru_hole oval (at 2.54 3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 5 thru_hole oval (at 0 3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 9 thru_hole oval (at 10.16 3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 10 thru_hole oval (at 10.16 -3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 11 thru_hole oval (at 7.62 -3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 12 thru_hole oval (at 5.08 -3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 13 thru_hole oval (at 2.54 -3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 14 thru_hole oval (at 0 -3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 15 thru_hole oval (at -2.54 -3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 16 thru_hole oval (at -5.08 -3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 17 thru_hole oval (at -7.62 -3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 18 thru_hole oval (at -10.16 -3.81 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+)
diff --git a/Schematic/C128-VRAM-64K-Expansion.pretty/DIL48.kicad_mod b/Schematic/C128-VRAM-64K-Expansion.pretty/DIL48.kicad_mod
new file mode 100644
index 0000000..e66055e
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion.pretty/DIL48.kicad_mod
@@ -0,0 +1,111 @@
+(module DIL48 (layer F.Cu) (tedit 0)
+  (descr "<b>Dual In Line Package</b>")
+  (fp_text reference IC2 (at -30.226 6.35 -270) (layer F.SilkS)
+    (effects (font (size 1.6891 1.6891) (thickness 0.16891)) (justify left bottom))
+  )
+  (fp_text value "" (at -16.637 1.016 -180) (layer F.Fab)
+    (effects (font (size 1.6891 1.6891) (thickness 0.16891)) (justify left bottom))
+  )
+  (fp_line (start -29.845 6.604) (end 29.845 6.604) (layer F.SilkS) (width 0.1524))
+  (fp_line (start 29.845 6.604) (end 29.845 -6.604) (layer F.SilkS) (width 0.1524))
+  (fp_line (start 29.845 -6.604) (end -29.845 -6.604) (layer F.SilkS) (width 0.1524))
+  (fp_line (start -29.845 -6.604) (end -29.845 -0.889) (layer F.SilkS) (width 0.1524))
+  (fp_line (start -29.845 6.604) (end -29.845 1.143) (layer F.SilkS) (width 0.1524))
+  (fp_arc (start -29.845 0.127) (end -29.845 -0.889) (angle 180) (layer F.SilkS) (width 0.1524))
+  (pad 1 thru_hole oval (at -29.21 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 2 thru_hole oval (at -26.67 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 3 thru_hole oval (at -24.13 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 4 thru_hole oval (at -21.59 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 5 thru_hole oval (at -19.05 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 6 thru_hole oval (at -16.51 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 7 thru_hole oval (at -13.97 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 8 thru_hole oval (at -11.43 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 9 thru_hole oval (at -8.89 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 10 thru_hole oval (at -6.35 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 11 thru_hole oval (at -3.81 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 12 thru_hole oval (at -1.27 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 13 thru_hole oval (at 1.27 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 14 thru_hole oval (at 3.81 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 15 thru_hole oval (at 6.35 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 16 thru_hole oval (at 8.89 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 17 thru_hole oval (at 11.43 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 18 thru_hole oval (at 13.97 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 19 thru_hole oval (at 16.51 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 20 thru_hole oval (at 19.05 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 21 thru_hole oval (at 21.59 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 22 thru_hole oval (at 24.13 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 23 thru_hole oval (at 26.67 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 24 thru_hole oval (at 29.21 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 25 thru_hole oval (at 29.21 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 26 thru_hole oval (at 26.67 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 27 thru_hole oval (at 24.13 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 28 thru_hole oval (at 21.59 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 29 thru_hole oval (at 19.05 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 30 thru_hole oval (at 16.51 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 31 thru_hole oval (at 13.97 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 32 thru_hole oval (at 11.43 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 33 thru_hole oval (at 8.89 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 34 thru_hole oval (at 6.35 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 35 thru_hole oval (at 3.81 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 36 thru_hole oval (at 1.27 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 37 thru_hole oval (at -1.27 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 38 thru_hole oval (at -3.81 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 39 thru_hole oval (at -6.35 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 40 thru_hole oval (at -8.89 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 41 thru_hole oval (at -11.43 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 42 thru_hole oval (at -13.97 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 43 thru_hole oval (at -16.51 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 44 thru_hole oval (at -19.05 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 45 thru_hole oval (at -21.59 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 46 thru_hole oval (at -24.13 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 47 thru_hole oval (at -26.67 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 48 thru_hole oval (at -29.21 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+)
diff --git a/Schematic/C128-VRAM-64K-Expansion.pretty/MOS8563.kicad_mod b/Schematic/C128-VRAM-64K-Expansion.pretty/MOS8563.kicad_mod
new file mode 100644
index 0000000..5d5676a
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion.pretty/MOS8563.kicad_mod
@@ -0,0 +1,111 @@
+(module MOS8563 (layer F.Cu) (tedit 0)
+  (descr "<b>Dual In Line Package</b>")
+  (fp_text reference IC1 (at -30.226 6.35 -270) (layer F.SilkS)
+    (effects (font (size 1.6891 1.6891) (thickness 0.16891)) (justify left bottom))
+  )
+  (fp_text value "" (at -16.637 1.016 -180) (layer F.Fab)
+    (effects (font (size 1.6891 1.6891) (thickness 0.16891)) (justify left bottom))
+  )
+  (fp_line (start -29.845 6.604) (end 29.845 6.604) (layer F.SilkS) (width 0.1524))
+  (fp_line (start 29.845 6.604) (end 29.845 -6.604) (layer F.SilkS) (width 0.1524))
+  (fp_line (start 29.845 -6.604) (end -29.845 -6.604) (layer F.SilkS) (width 0.1524))
+  (fp_line (start -29.845 -6.604) (end -29.845 -0.889) (layer F.SilkS) (width 0.1524))
+  (fp_line (start -29.845 6.604) (end -29.845 1.143) (layer F.SilkS) (width 0.1524))
+  (fp_arc (start -29.845 0.127) (end -29.845 -0.889) (angle 180) (layer F.SilkS) (width 0.1524))
+  (pad 1 thru_hole oval (at -29.21 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 2 thru_hole oval (at -26.67 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 3 thru_hole oval (at -24.13 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 4 thru_hole oval (at -21.59 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 5 thru_hole oval (at -19.05 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 6 thru_hole oval (at -16.51 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 7 thru_hole oval (at -13.97 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 8 thru_hole oval (at -11.43 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 9 thru_hole oval (at -8.89 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 10 thru_hole oval (at -6.35 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 11 thru_hole oval (at -3.81 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 12 thru_hole oval (at -1.27 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 13 thru_hole oval (at 1.27 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 14 thru_hole oval (at 3.81 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 15 thru_hole oval (at 6.35 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 16 thru_hole oval (at 8.89 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 17 thru_hole oval (at 11.43 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 18 thru_hole oval (at 13.97 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 19 thru_hole oval (at 16.51 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 20 thru_hole oval (at 19.05 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 21 thru_hole oval (at 21.59 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 22 thru_hole oval (at 24.13 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 23 thru_hole oval (at 26.67 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 24 thru_hole oval (at 29.21 7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 25 thru_hole oval (at 29.21 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 26 thru_hole oval (at 26.67 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 27 thru_hole oval (at 24.13 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 28 thru_hole oval (at 21.59 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 29 thru_hole oval (at 19.05 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 30 thru_hole oval (at 16.51 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 31 thru_hole oval (at 13.97 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 32 thru_hole oval (at 11.43 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 33 thru_hole oval (at 8.89 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 34 thru_hole oval (at 6.35 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 35 thru_hole oval (at 3.81 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 36 thru_hole oval (at 1.27 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 37 thru_hole oval (at -1.27 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 38 thru_hole oval (at -3.81 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 39 thru_hole oval (at -6.35 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 40 thru_hole oval (at -8.89 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 41 thru_hole oval (at -11.43 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 42 thru_hole oval (at -13.97 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 43 thru_hole oval (at -16.51 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 44 thru_hole oval (at -19.05 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 45 thru_hole oval (at -21.59 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 46 thru_hole oval (at -24.13 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 47 thru_hole oval (at -26.67 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+  (pad 48 thru_hole oval (at -29.21 -7.62 90) (size 2.6416 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
+    (solder_mask_margin 0.1016))
+)
diff --git a/Schematic/C128-VRAM-64K-Expansion.pro b/Schematic/C128-VRAM-64K-Expansion.pro
new file mode 100644
index 0000000..98a6099
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion.pro
@@ -0,0 +1,259 @@
+update=01/10/21 21:45:14
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=empty.kicad_wks
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.1524
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.262672
+TrackWidth1=0.25
+ViaDiameter1=0.8
+ViaDrill1=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.09999999999999999
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0
+SolderMaskMinWidth=0
+SolderPasteClearance=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=Top
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
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+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=Bottom
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
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+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
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+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
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+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
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+[pcbnew/Layer.F.CrtYd]
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+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.1524
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
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+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=Power
+Clearance=0.1524
+TrackWidth=0.5
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
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+dPairWidth=0.2
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diff --git a/Schematic/C128-VRAM-64K-Expansion.sch b/Schematic/C128-VRAM-64K-Expansion.sch
new file mode 100644
index 0000000..ebe0e0e
--- /dev/null
+++ b/Schematic/C128-VRAM-64K-Expansion.sch
@@ -0,0 +1,852 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr User 11774 8268
+encoding utf-8
+Sheet 1 1
+Title "RCEU2364 C128 64KB VRAM"
+Date "2021-02-03"
+Rev "v1.2"
+Comp "https://retro-commodore.eu"
+Comment1 ""
+Comment2 ""
+Comment3 "Copyright (c) 2018-2021"
+Comment4 "by Tomse"
+$EndDescr
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+GND
+NoConn ~ 3800 2600
+NoConn ~ 3800 2700
+Text Label 7800 1400 0    50   ~ 0
+DD2
+Text Label 7800 1500 0    50   ~ 0
+DD1
+Text Label 7800 1600 0    50   ~ 0
+DD0
+Text Label 7800 1300 0    50   ~ 0
+DD3
+Text Label 7800 1000 0    50   ~ 0
+DD6
+Text Label 7800 1100 0    50   ~ 0
+DD5
+Text Label 7800 1200 0    50   ~ 0
+DD4
+Text Label 7800 900  0    50   ~ 0
+DD7
+Wire Wire Line
+	8100 1300 8100 3200
+Wire Wire Line
+	2500 2800 2800 2800
+Wire Wire Line
+	2500 3400 3300 3400
+Wire Bus Line
+	2600 2200 2600 4700
+Wire Bus Line
+	4500 2200 4500 4700
+Wire Bus Line
+	1300 2000 1300 4500
+Wire Bus Line
+	3700 2000 3700 4500
+$EndSCHEMATC
diff --git a/Schematic/fp-info-cache b/Schematic/fp-info-cache
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/Schematic/fp-info-cache
@@ -0,0 +1 @@
+0
diff --git a/Schematic/sym-lib-table b/Schematic/sym-lib-table
new file mode 100644
index 0000000..78822ab
--- /dev/null
+++ b/Schematic/sym-lib-table
@@ -0,0 +1,3 @@
+(sym_lib_table
+  (lib (name C128-VRAM-64K-Expansion-rescue)(type Legacy)(uri ${KIPRJMOD}/C128-VRAM-64K-Expansion-rescue.lib)(options "")(descr ""))
+)